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hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
Connect the Configuration Frame controller (CFRAME_REG) and the Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the Versal machine. Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230831165701.2016397-9-francisco.iglesias@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2 changed files with 181 additions and 1 deletions
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@ -33,6 +33,7 @@
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#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
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#include "hw/net/xlnx-versal-canfd.h"
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#include "hw/misc/xlnx-versal-cfu.h"
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#include "hw/misc/xlnx-versal-cframe-reg.h"
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#define TYPE_XLNX_VERSAL "xlnx-versal"
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OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
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@ -47,6 +48,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
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#define XLNX_VERSAL_NR_IRQS 192
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#define XLNX_VERSAL_NR_CANFD 2
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#define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000)
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#define XLNX_VERSAL_NR_CFRAME 15
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struct Versal {
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/*< private >*/
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@ -121,6 +123,8 @@ struct Versal {
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XlnxVersalCFUAPB cfu_apb;
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XlnxVersalCFUFDRO cfu_fdro;
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XlnxVersalCFUSFR cfu_sfr;
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XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME];
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XlnxVersalCFrameBcastReg cframe_bcast;
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OrIRQState apb_irq_orgate;
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} pmc;
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@ -256,6 +260,71 @@ struct Versal {
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#define MM_PMC_CFU_STREAM_2 0xf1f80000
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#define MM_PMC_CFU_STREAM_2_SIZE 0x40000
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#define MM_PMC_CFRAME0_REG 0xf12d0000
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#define MM_PMC_CFRAME0_REG_SIZE 0x1000
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#define MM_PMC_CFRAME0_FDRI 0xf12d1000
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#define MM_PMC_CFRAME0_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME1_REG 0xf12d2000
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#define MM_PMC_CFRAME1_REG_SIZE 0x1000
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#define MM_PMC_CFRAME1_FDRI 0xf12d3000
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#define MM_PMC_CFRAME1_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME2_REG 0xf12d4000
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#define MM_PMC_CFRAME2_REG_SIZE 0x1000
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#define MM_PMC_CFRAME2_FDRI 0xf12d5000
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#define MM_PMC_CFRAME2_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME3_REG 0xf12d6000
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#define MM_PMC_CFRAME3_REG_SIZE 0x1000
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#define MM_PMC_CFRAME3_FDRI 0xf12d7000
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#define MM_PMC_CFRAME3_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME4_REG 0xf12d8000
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#define MM_PMC_CFRAME4_REG_SIZE 0x1000
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#define MM_PMC_CFRAME4_FDRI 0xf12d9000
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#define MM_PMC_CFRAME4_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME5_REG 0xf12da000
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#define MM_PMC_CFRAME5_REG_SIZE 0x1000
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#define MM_PMC_CFRAME5_FDRI 0xf12db000
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#define MM_PMC_CFRAME5_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME6_REG 0xf12dc000
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#define MM_PMC_CFRAME6_REG_SIZE 0x1000
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#define MM_PMC_CFRAME6_FDRI 0xf12dd000
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#define MM_PMC_CFRAME6_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME7_REG 0xf12de000
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#define MM_PMC_CFRAME7_REG_SIZE 0x1000
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#define MM_PMC_CFRAME7_FDRI 0xf12df000
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#define MM_PMC_CFRAME7_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME8_REG 0xf12e0000
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#define MM_PMC_CFRAME8_REG_SIZE 0x1000
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#define MM_PMC_CFRAME8_FDRI 0xf12e1000
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#define MM_PMC_CFRAME8_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME9_REG 0xf12e2000
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#define MM_PMC_CFRAME9_REG_SIZE 0x1000
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#define MM_PMC_CFRAME9_FDRI 0xf12e3000
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#define MM_PMC_CFRAME9_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME10_REG 0xf12e4000
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#define MM_PMC_CFRAME10_REG_SIZE 0x1000
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#define MM_PMC_CFRAME10_FDRI 0xf12e5000
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#define MM_PMC_CFRAME10_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME11_REG 0xf12e6000
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#define MM_PMC_CFRAME11_REG_SIZE 0x1000
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#define MM_PMC_CFRAME11_FDRI 0xf12e7000
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#define MM_PMC_CFRAME11_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME12_REG 0xf12e8000
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#define MM_PMC_CFRAME12_REG_SIZE 0x1000
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#define MM_PMC_CFRAME12_FDRI 0xf12e9000
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#define MM_PMC_CFRAME12_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME13_REG 0xf12ea000
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#define MM_PMC_CFRAME13_REG_SIZE 0x1000
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#define MM_PMC_CFRAME13_FDRI 0xf12eb000
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#define MM_PMC_CFRAME13_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME14_REG 0xf12ec000
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#define MM_PMC_CFRAME14_REG_SIZE 0x1000
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#define MM_PMC_CFRAME14_FDRI 0xf12ed000
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#define MM_PMC_CFRAME14_FDRI_SIZE 0x1000
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#define MM_PMC_CFRAME_BCAST_REG 0xf12ee000
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#define MM_PMC_CFRAME_BCAST_REG_SIZE 0x1000
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#define MM_PMC_CFRAME_BCAST_FDRI 0xf12ef000
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#define MM_PMC_CFRAME_BCAST_FDRI_SIZE 0x1000
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#define MM_PMC_CRP 0xf1260000U
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#define MM_PMC_CRP_SIZE 0x10000
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#define MM_PMC_RTC 0xf12a0000
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