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https://github.com/Motorhead1991/qemu.git
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hw: move target-independent files to subdirectories
This patch tackles all files that are compiled once, moving them to subdirectories of hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
ce3b494cb5
commit
49ab747f66
227 changed files with 205 additions and 208 deletions
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@ -0,0 +1,2 @@
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common-obj-$(CONFIG_PL022) += pl022.o
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common-obj-$(CONFIG_SSI) += ssi.o
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308
hw/ssi/pl022.c
Normal file
308
hw/ssi/pl022.c
Normal file
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@ -0,0 +1,308 @@
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/*
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* Arm PrimeCell PL022 Synchronous Serial Port
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/sysbus.h"
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#include "hw/ssi.h"
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//#define DEBUG_PL022 1
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#ifdef DEBUG_PL022
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#define DPRINTF(fmt, ...) \
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do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
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#endif
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#define PL022_CR1_LBM 0x01
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#define PL022_CR1_SSE 0x02
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#define PL022_CR1_MS 0x04
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#define PL022_CR1_SDO 0x08
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#define PL022_SR_TFE 0x01
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#define PL022_SR_TNF 0x02
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#define PL022_SR_RNE 0x04
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#define PL022_SR_RFF 0x08
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#define PL022_SR_BSY 0x10
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#define PL022_INT_ROR 0x01
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#define PL022_INT_RT 0x04
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#define PL022_INT_RX 0x04
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#define PL022_INT_TX 0x08
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t cr0;
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uint32_t cr1;
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uint32_t bitmask;
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uint32_t sr;
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uint32_t cpsr;
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uint32_t is;
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uint32_t im;
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/* The FIFO head points to the next empty entry. */
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int tx_fifo_head;
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int rx_fifo_head;
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int tx_fifo_len;
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int rx_fifo_len;
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uint16_t tx_fifo[8];
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uint16_t rx_fifo[8];
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qemu_irq irq;
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SSIBus *ssi;
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} pl022_state;
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static const unsigned char pl022_id[8] =
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{ 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static void pl022_update(pl022_state *s)
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{
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s->sr = 0;
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if (s->tx_fifo_len == 0)
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s->sr |= PL022_SR_TFE;
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if (s->tx_fifo_len != 8)
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s->sr |= PL022_SR_TNF;
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if (s->rx_fifo_len != 0)
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s->sr |= PL022_SR_RNE;
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if (s->rx_fifo_len == 8)
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s->sr |= PL022_SR_RFF;
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if (s->tx_fifo_len)
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s->sr |= PL022_SR_BSY;
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s->is = 0;
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if (s->rx_fifo_len >= 4)
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s->is |= PL022_INT_RX;
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if (s->tx_fifo_len <= 4)
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s->is |= PL022_INT_TX;
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qemu_set_irq(s->irq, (s->is & s->im) != 0);
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}
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static void pl022_xfer(pl022_state *s)
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{
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int i;
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int o;
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int val;
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if ((s->cr1 & PL022_CR1_SSE) == 0) {
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pl022_update(s);
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DPRINTF("Disabled\n");
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return;
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}
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DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
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i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
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o = s->rx_fifo_head;
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/* ??? We do not emulate the line speed.
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This may break some applications. The are two problematic cases:
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(a) A driver feeds data into the TX FIFO until it is full,
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and only then drains the RX FIFO. On real hardware the CPU can
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feed data fast enough that the RX fifo never gets chance to overflow.
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(b) A driver transmits data, deliberately allowing the RX FIFO to
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overflow because it ignores the RX data anyway.
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We choose to support (a) by stalling the transmit engine if it would
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cause the RX FIFO to overflow. In practice much transmit-only code
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falls into (a) because it flushes the RX FIFO to determine when
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the transfer has completed. */
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while (s->tx_fifo_len && s->rx_fifo_len < 8) {
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DPRINTF("xfer\n");
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val = s->tx_fifo[i];
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if (s->cr1 & PL022_CR1_LBM) {
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/* Loopback mode. */
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} else {
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val = ssi_transfer(s->ssi, val);
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}
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s->rx_fifo[o] = val & s->bitmask;
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i = (i + 1) & 7;
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o = (o + 1) & 7;
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s->tx_fifo_len--;
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s->rx_fifo_len++;
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}
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s->rx_fifo_head = o;
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pl022_update(s);
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}
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static uint64_t pl022_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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pl022_state *s = (pl022_state *)opaque;
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int val;
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if (offset >= 0xfe0 && offset < 0x1000) {
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return pl022_id[(offset - 0xfe0) >> 2];
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}
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switch (offset) {
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case 0x00: /* CR0 */
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return s->cr0;
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case 0x04: /* CR1 */
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return s->cr1;
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case 0x08: /* DR */
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if (s->rx_fifo_len) {
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val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
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DPRINTF("RX %02x\n", val);
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s->rx_fifo_len--;
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pl022_xfer(s);
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} else {
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val = 0;
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}
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return val;
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case 0x0c: /* SR */
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return s->sr;
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case 0x10: /* CPSR */
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return s->cpsr;
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case 0x14: /* IMSC */
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return s->im;
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case 0x18: /* RIS */
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return s->is;
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case 0x1c: /* MIS */
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return s->im & s->is;
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case 0x20: /* DMACR */
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/* Not implemented. */
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl022_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void pl022_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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pl022_state *s = (pl022_state *)opaque;
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switch (offset) {
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case 0x00: /* CR0 */
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s->cr0 = value;
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/* Clock rate and format are ignored. */
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s->bitmask = (1 << ((value & 15) + 1)) - 1;
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break;
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case 0x04: /* CR1 */
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s->cr1 = value;
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if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE))
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== (PL022_CR1_MS | PL022_CR1_SSE)) {
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BADF("SPI slave mode not implemented\n");
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}
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pl022_xfer(s);
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break;
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case 0x08: /* DR */
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if (s->tx_fifo_len < 8) {
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DPRINTF("TX %02x\n", (unsigned)value);
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s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
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s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
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s->tx_fifo_len++;
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pl022_xfer(s);
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}
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break;
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case 0x10: /* CPSR */
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/* Prescaler. Ignored. */
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s->cpsr = value & 0xff;
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break;
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case 0x14: /* IMSC */
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s->im = value;
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pl022_update(s);
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break;
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case 0x20: /* DMACR */
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if (value) {
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qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl022_write: Bad offset %x\n", (int)offset);
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}
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}
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static void pl022_reset(pl022_state *s)
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{
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s->rx_fifo_len = 0;
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s->tx_fifo_len = 0;
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s->im = 0;
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s->is = PL022_INT_TX;
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s->sr = PL022_SR_TFE | PL022_SR_TNF;
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}
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static const MemoryRegionOps pl022_ops = {
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.read = pl022_read,
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.write = pl022_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_pl022 = {
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.name = "pl022_ssp",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr0, pl022_state),
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VMSTATE_UINT32(cr1, pl022_state),
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VMSTATE_UINT32(bitmask, pl022_state),
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VMSTATE_UINT32(sr, pl022_state),
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VMSTATE_UINT32(cpsr, pl022_state),
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VMSTATE_UINT32(is, pl022_state),
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VMSTATE_UINT32(im, pl022_state),
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VMSTATE_INT32(tx_fifo_head, pl022_state),
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VMSTATE_INT32(rx_fifo_head, pl022_state),
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VMSTATE_INT32(tx_fifo_len, pl022_state),
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VMSTATE_INT32(rx_fifo_len, pl022_state),
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VMSTATE_UINT16(tx_fifo[0], pl022_state),
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VMSTATE_UINT16(rx_fifo[0], pl022_state),
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VMSTATE_UINT16(tx_fifo[1], pl022_state),
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VMSTATE_UINT16(rx_fifo[1], pl022_state),
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VMSTATE_UINT16(tx_fifo[2], pl022_state),
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VMSTATE_UINT16(rx_fifo[2], pl022_state),
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VMSTATE_UINT16(tx_fifo[3], pl022_state),
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VMSTATE_UINT16(rx_fifo[3], pl022_state),
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VMSTATE_UINT16(tx_fifo[4], pl022_state),
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VMSTATE_UINT16(rx_fifo[4], pl022_state),
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VMSTATE_UINT16(tx_fifo[5], pl022_state),
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VMSTATE_UINT16(rx_fifo[5], pl022_state),
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VMSTATE_UINT16(tx_fifo[6], pl022_state),
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VMSTATE_UINT16(rx_fifo[6], pl022_state),
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VMSTATE_UINT16(tx_fifo[7], pl022_state),
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VMSTATE_UINT16(rx_fifo[7], pl022_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static int pl022_init(SysBusDevice *dev)
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{
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pl022_state *s = FROM_SYSBUS(pl022_state, dev);
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memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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s->ssi = ssi_create_bus(&dev->qdev, "ssi");
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pl022_reset(s);
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vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
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return 0;
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}
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static void pl022_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = pl022_init;
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}
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static const TypeInfo pl022_info = {
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.name = "pl022",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(pl022_state),
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.class_init = pl022_class_init,
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};
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static void pl022_register_types(void)
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{
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type_register_static(&pl022_info);
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}
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type_init(pl022_register_types)
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174
hw/ssi/ssi.c
Normal file
174
hw/ssi/ssi.c
Normal file
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@ -0,0 +1,174 @@
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/*
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* QEMU Synchronous Serial Interface support
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*
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* Copyright (c) 2009 CodeSourcery.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Written by Paul Brook
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*
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* This code is licensed under the GNU GPL v2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw/ssi.h"
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struct SSIBus {
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BusState qbus;
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};
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#define TYPE_SSI_BUS "SSI"
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#define SSI_BUS(obj) OBJECT_CHECK(SSIBus, (obj), TYPE_SSI_BUS)
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static const TypeInfo ssi_bus_info = {
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.name = TYPE_SSI_BUS,
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.parent = TYPE_BUS,
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.instance_size = sizeof(SSIBus),
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};
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static void ssi_cs_default(void *opaque, int n, int level)
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{
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SSISlave *s = SSI_SLAVE(opaque);
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bool cs = !!level;
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assert(n == 0);
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if (s->cs != cs) {
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SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
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if (ssc->set_cs) {
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ssc->set_cs(s, cs);
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}
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}
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s->cs = cs;
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}
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static uint32_t ssi_transfer_raw_default(SSISlave *dev, uint32_t val)
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{
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SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(dev);
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if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
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(!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
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ssc->cs_polarity == SSI_CS_NONE) {
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return ssc->transfer(dev, val);
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}
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return 0;
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}
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static int ssi_slave_init(DeviceState *dev)
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{
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SSISlave *s = SSI_SLAVE(dev);
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SSISlaveClass *ssc = SSI_SLAVE_GET_CLASS(s);
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if (ssc->transfer_raw == ssi_transfer_raw_default &&
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ssc->cs_polarity != SSI_CS_NONE) {
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qdev_init_gpio_in(&s->qdev, ssi_cs_default, 1);
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}
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return ssc->init(s);
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}
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static void ssi_slave_class_init(ObjectClass *klass, void *data)
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{
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SSISlaveClass *ssc = SSI_SLAVE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->init = ssi_slave_init;
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dc->bus_type = TYPE_SSI_BUS;
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if (!ssc->transfer_raw) {
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ssc->transfer_raw = ssi_transfer_raw_default;
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}
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}
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static const TypeInfo ssi_slave_info = {
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.name = TYPE_SSI_SLAVE,
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.parent = TYPE_DEVICE,
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.class_init = ssi_slave_class_init,
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.class_size = sizeof(SSISlaveClass),
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.abstract = true,
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};
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DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name)
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{
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return qdev_create(&bus->qbus, name);
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}
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DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
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{
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DeviceState *dev = ssi_create_slave_no_init(bus, name);
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qdev_init_nofail(dev);
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return dev;
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}
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SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
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{
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BusState *bus;
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bus = qbus_create(TYPE_SSI_BUS, parent, name);
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return FROM_QBUS(SSIBus, bus);
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}
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uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
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{
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BusChild *kid;
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SSISlaveClass *ssc;
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uint32_t r = 0;
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QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
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SSISlave *slave = SSI_SLAVE(kid->child);
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ssc = SSI_SLAVE_GET_CLASS(slave);
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r |= ssc->transfer_raw(slave, val);
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}
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return r;
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}
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const VMStateDescription vmstate_ssi_slave = {
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.name = "SSISlave",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(cs, SSISlave),
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VMSTATE_END_OF_LIST()
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}
|
||||
};
|
||||
|
||||
static void ssi_slave_register_types(void)
|
||||
{
|
||||
type_register_static(&ssi_bus_info);
|
||||
type_register_static(&ssi_slave_info);
|
||||
}
|
||||
|
||||
type_init(ssi_slave_register_types)
|
||||
|
||||
typedef struct SSIAutoConnectArg {
|
||||
qemu_irq **cs_linep;
|
||||
SSIBus *bus;
|
||||
} SSIAutoConnectArg;
|
||||
|
||||
static int ssi_auto_connect_slave(Object *child, void *opaque)
|
||||
{
|
||||
SSIAutoConnectArg *arg = opaque;
|
||||
SSISlave *dev = (SSISlave *)object_dynamic_cast(child, TYPE_SSI_SLAVE);
|
||||
qemu_irq cs_line;
|
||||
|
||||
if (!dev) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
cs_line = qdev_get_gpio_in(DEVICE(dev), 0);
|
||||
qdev_set_parent_bus(DEVICE(dev), &arg->bus->qbus);
|
||||
**arg->cs_linep = cs_line;
|
||||
(*arg->cs_linep)++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_line,
|
||||
SSIBus *bus)
|
||||
{
|
||||
SSIAutoConnectArg arg = {
|
||||
.cs_linep = &cs_line,
|
||||
.bus = bus
|
||||
};
|
||||
|
||||
object_child_foreach(OBJECT(parent), ssi_auto_connect_slave, &arg);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue