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hw: move target-independent files to subdirectories

Browse source 
This patch tackles all files that are compiled once, moving
them to subdirectories of hw/.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2013-03-01 13:59:19 +01:00
parent ce3b494cb5
commit 49ab747f66
227 changed files with 205 additions and 208 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/nvram/Makefile.objs
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common-obj-$(CONFIG_DS1225Y) += ds1225y.o
common-obj-y += eeprom93xx.o
common-obj-y += fw_cfg.o
common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o

165
hw/nvram/ds1225y.c Normal file
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/*
* QEMU NVRAM emulation for DS1225Y chip
*
* Copyright (c) 2007-2008 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/sysbus.h"
#include "trace.h"
typedef struct {
DeviceState qdev;
MemoryRegion iomem;
uint32_t chip_size;
char *filename;
FILE *file;
uint8_t *contents;
} NvRamState;
static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
val = s->contents[addr];
trace_nvram_read(addr, val);
return val;
}
static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;
val &= 0xff;
trace_nvram_write(addr, s->contents[addr], val);
s->contents[addr] = val;
if (s->file) {
fseek(s->file, addr, SEEK_SET);
fputc(val, s->file);
fflush(s->file);
}
}
static const MemoryRegionOps nvram_ops = {
.read = nvram_read,
.write = nvram_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int nvram_post_load(void *opaque, int version_id)
{
NvRamState *s = opaque;
/* Close file, as filename may has changed in load/store process */
if (s->file) {
fclose(s->file);
}
/* Write back nvram contents */
s->file = fopen(s->filename, "wb");
if (s->file) {
/* Write back contents, as 'wb' mode cleaned the file */
if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) {
printf("nvram_post_load: short write\n");
}
fflush(s->file);
}
return 0;
}
static const VMStateDescription vmstate_nvram = {
.name = "nvram",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.post_load = nvram_post_load,
.fields = (VMStateField[]) {
VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
vmstate_info_uint8, uint8_t),
VMSTATE_END_OF_LIST()
}
};
typedef struct {
SysBusDevice busdev;
NvRamState nvram;
} SysBusNvRamState;
static int nvram_sysbus_initfn(SysBusDevice *dev)
{
NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
FILE *file;
s->contents = g_malloc0(s->chip_size);
memory_region_init_io(&s->iomem, &nvram_ops, s, "nvram", s->chip_size);
sysbus_init_mmio(dev, &s->iomem);
/* Read current file */
file = fopen(s->filename, "rb");
if (file) {
/* Read nvram contents */
if (fread(s->contents, s->chip_size, 1, file) != 1) {
printf("nvram_sysbus_initfn: short read\n");
}
fclose(file);
}
nvram_post_load(s, 0);
return 0;
}
static Property nvram_sysbus_properties[] = {
DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
DEFINE_PROP_END_OF_LIST(),
};
static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = nvram_sysbus_initfn;
dc->vmsd = &vmstate_nvram;
dc->props = nvram_sysbus_properties;
}
static const TypeInfo nvram_sysbus_info = {
.name = "ds1225y",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SysBusNvRamState),
.class_init = nvram_sysbus_class_init,
};
static void nvram_register_types(void)
{
type_register_static(&nvram_sysbus_info);
}
type_init(nvram_register_types)

337
hw/nvram/eeprom93xx.c Normal file
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/*
* QEMU EEPROM 93xx emulation
*
* Copyright (c) 2006-2007 Stefan Weil
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
/* Emulation for serial EEPROMs:
* NMC93C06 256-Bit (16 x 16)
* NMC93C46 1024-Bit (64 x 16)
* NMC93C56 2028 Bit (128 x 16)
* NMC93C66 4096 Bit (256 x 16)
* Compatible devices include FM93C46 and others.
*
* Other drivers use these interface functions:
* eeprom93xx_new - add a new EEPROM (with 16, 64 or 256 words)
* eeprom93xx_free - destroy EEPROM
* eeprom93xx_read - read data from the EEPROM
* eeprom93xx_write - write data to the EEPROM
* eeprom93xx_data - get EEPROM data array for external manipulation
*
* Todo list:
* - No emulation of EEPROM timings.
*/
#include "hw/hw.h"
#include "hw/nvram/eeprom93xx.h"
/* Debug EEPROM emulation. */
//~ #define DEBUG_EEPROM
#ifdef DEBUG_EEPROM
#define logout(fmt, ...) fprintf(stderr, "EEPROM\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else
#define logout(fmt, ...) ((void)0)
#endif
#define EEPROM_INSTANCE 0
#define OLD_EEPROM_VERSION 20061112
#define EEPROM_VERSION (OLD_EEPROM_VERSION + 1)
#if 0
typedef enum {
eeprom_read = 0x80, /* read register xx */
eeprom_write = 0x40, /* write register xx */
eeprom_erase = 0xc0, /* erase register xx */
eeprom_ewen = 0x30, /* erase / write enable */
eeprom_ewds = 0x00, /* erase / write disable */
eeprom_eral = 0x20, /* erase all registers */
eeprom_wral = 0x10, /* write all registers */
eeprom_amask = 0x0f,
eeprom_imask = 0xf0
} eeprom_instruction_t;
#endif
#ifdef DEBUG_EEPROM
static const char *opstring[] = {
"extended", "write", "read", "erase"
};
#endif
struct _eeprom_t {
uint8_t tick;
uint8_t address;
uint8_t command;
uint8_t writable;
uint8_t eecs;
uint8_t eesk;
uint8_t eedo;
uint8_t addrbits;
uint16_t size;
uint16_t data;
uint16_t contents[0];
};
/* Code for saving and restoring of EEPROM state. */
/* Restore an uint16_t from an uint8_t
This is a Big hack, but it is how the old state did it.
*/
static int get_uint16_from_uint8(QEMUFile *f, void *pv, size_t size)
{
uint16_t *v = pv;
*v = qemu_get_ubyte(f);
return 0;
}
static void put_unused(QEMUFile *f, void *pv, size_t size)
{
fprintf(stderr, "uint16_from_uint8 is used only for backwards compatibility.\n");
fprintf(stderr, "Never should be used to write a new state.\n");
exit(0);
}
static const VMStateInfo vmstate_hack_uint16_from_uint8 = {
.name = "uint16_from_uint8",
.get = get_uint16_from_uint8,
.put = put_unused,
};
#define VMSTATE_UINT16_HACK_TEST(_f, _s, _t) \
VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint16_from_uint8, uint16_t)
static bool is_old_eeprom_version(void *opaque, int version_id)
{
return version_id == OLD_EEPROM_VERSION;
}
static const VMStateDescription vmstate_eeprom = {
.name = "eeprom",
.version_id = EEPROM_VERSION,
.minimum_version_id = OLD_EEPROM_VERSION,
.minimum_version_id_old = OLD_EEPROM_VERSION,
.fields = (VMStateField []) {
VMSTATE_UINT8(tick, eeprom_t),
VMSTATE_UINT8(address, eeprom_t),
VMSTATE_UINT8(command, eeprom_t),
VMSTATE_UINT8(writable, eeprom_t),
VMSTATE_UINT8(eecs, eeprom_t),
VMSTATE_UINT8(eesk, eeprom_t),
VMSTATE_UINT8(eedo, eeprom_t),
VMSTATE_UINT8(addrbits, eeprom_t),
VMSTATE_UINT16_HACK_TEST(size, eeprom_t, is_old_eeprom_version),
VMSTATE_UNUSED_TEST(is_old_eeprom_version, 1),
VMSTATE_UINT16_EQUAL_V(size, eeprom_t, EEPROM_VERSION),
VMSTATE_UINT16(data, eeprom_t),
VMSTATE_VARRAY_UINT16_UNSAFE(contents, eeprom_t, size, 0,
vmstate_info_uint16, uint16_t),
VMSTATE_END_OF_LIST()
}
};
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->tick;
uint8_t eedo = eeprom->eedo;
uint16_t address = eeprom->address;
uint8_t command = eeprom->command;
logout("CS=%u SK=%u DI=%u DO=%u, tick = %u\n",
eecs, eesk, eedi, eedo, tick);
if (! eeprom->eecs && eecs) {
/* Start chip select cycle. */
logout("Cycle start, waiting for 1st start bit (0)\n");
tick = 0;
command = 0x0;
address = 0x0;
} else if (eeprom->eecs && ! eecs) {
/* End chip select cycle. This triggers write / erase. */
if (eeprom->writable) {
uint8_t subcommand = address >> (eeprom->addrbits - 2);
if (command == 0 && subcommand == 2) {
/* Erase all. */
for (address = 0; address < eeprom->size; address++) {
eeprom->contents[address] = 0xffff;
}
} else if (command == 3) {
/* Erase word. */
eeprom->contents[address] = 0xffff;
} else if (tick >= 2 + 2 + eeprom->addrbits + 16) {
if (command == 1) {
/* Write word. */
eeprom->contents[address] &= eeprom->data;
} else if (command == 0 && subcommand == 1) {
/* Write all. */
for (address = 0; address < eeprom->size; address++) {
eeprom->contents[address] &= eeprom->data;
}
}
}
}
/* Output DO is tristate, read results in 1. */
eedo = 1;
} else if (eecs && ! eeprom->eesk && eesk) {
/* Raising edge of clock shifts data in. */
if (tick == 0) {
/* Wait for 1st start bit. */
if (eedi == 0) {
logout("Got correct 1st start bit, waiting for 2nd start bit (1)\n");
tick++;
} else {
logout("wrong 1st start bit (is 1, should be 0)\n");
tick = 2;
//~ assert(!"wrong start bit");
}
} else if (tick == 1) {
/* Wait for 2nd start bit. */
if (eedi != 0) {
logout("Got correct 2nd start bit, getting command + address\n");
tick++;
} else {
logout("1st start bit is longer than needed\n");
}
} else if (tick < 2 + 2) {
/* Got 2 start bits, transfer 2 opcode bits. */
tick++;
command <<= 1;
if (eedi) {
command += 1;
}
} else if (tick < 2 + 2 + eeprom->addrbits) {
/* Got 2 start bits and 2 opcode bits, transfer all address bits. */
tick++;
address = ((address << 1) | eedi);
if (tick == 2 + 2 + eeprom->addrbits) {
logout("%s command, address = 0x%02x (value 0x%04x)\n",
opstring[command], address, eeprom->contents[address]);
if (command == 2) {
eedo = 0;
}
address = address % eeprom->size;
if (command == 0) {
/* Command code in upper 2 bits of address. */
switch (address >> (eeprom->addrbits - 2)) {
case 0:
logout("write disable command\n");
eeprom->writable = 0;
break;
case 1:
logout("write all command\n");
break;
case 2:
logout("erase all command\n");
break;
case 3:
logout("write enable command\n");
eeprom->writable = 1;
break;
}
} else {
/* Read, write or erase word. */
eeprom->data = eeprom->contents[address];
}
}
} else if (tick < 2 + 2 + eeprom->addrbits + 16) {
/* Transfer 16 data bits. */
tick++;
if (command == 2) {
/* Read word. */
eedo = ((eeprom->data & 0x8000) != 0);
}
eeprom->data <<= 1;
eeprom->data += eedi;
} else {
logout("additional unneeded tick, not processed\n");
}
}
/* Save status of EEPROM. */
eeprom->tick = tick;
eeprom->eecs = eecs;
eeprom->eesk = eesk;
eeprom->eedo = eedo;
eeprom->address = address;
eeprom->command = command;
}
uint16_t eeprom93xx_read(eeprom_t *eeprom)
{
/* Return status of pin DO (0 or 1). */
logout("CS=%u DO=%u\n", eeprom->eecs, eeprom->eedo);
return (eeprom->eedo);
}
#if 0
void eeprom93xx_reset(eeprom_t *eeprom)
{
/* prepare eeprom */
logout("eeprom = 0x%p\n", eeprom);
eeprom->tick = 0;
eeprom->command = 0;
}
#endif
eeprom_t *eeprom93xx_new(DeviceState *dev, uint16_t nwords)
{
/* Add a new EEPROM (with 16, 64 or 256 words). */
eeprom_t *eeprom;
uint8_t addrbits;
switch (nwords) {
case 16:
case 64:
addrbits = 6;
break;
case 128:
case 256:
addrbits = 8;
break;
default:
assert(!"Unsupported EEPROM size, fallback to 64 words!");
nwords = 64;
addrbits = 6;
}
eeprom = (eeprom_t *)g_malloc0(sizeof(*eeprom) + nwords * 2);
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
eeprom->eedo = 1;
logout("eeprom = 0x%p, nwords = %u\n", eeprom, nwords);
vmstate_register(dev, 0, &vmstate_eeprom, eeprom);
return eeprom;
}
void eeprom93xx_free(DeviceState *dev, eeprom_t *eeprom)
{
/* Destroy EEPROM. */
logout("eeprom = 0x%p\n", eeprom);
vmstate_unregister(dev, &vmstate_eeprom, eeprom);
g_free(eeprom);
}
uint16_t *eeprom93xx_data(eeprom_t *eeprom)
{
/* Get EEPROM data array. */
return &eeprom->contents[0];
}
/* eof */

574
hw/nvram/fw_cfg.c Normal file
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/*
* QEMU Firmware configuration device emulation
*
* Copyright (c) 2008 Gleb Natapov
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/hw.h"
#include "sysemu/sysemu.h"
#include "hw/isa/isa.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/sysbus.h"
#include "trace.h"
#include "qemu/error-report.h"
#include "qemu/config-file.h"
#define FW_CFG_SIZE 2
#define FW_CFG_DATA_SIZE 1
typedef struct FWCfgEntry {
uint32_t len;
uint8_t *data;
void *callback_opaque;
FWCfgCallback callback;
} FWCfgEntry;
struct FWCfgState {
SysBusDevice busdev;
MemoryRegion ctl_iomem, data_iomem, comb_iomem;
uint32_t ctl_iobase, data_iobase;
FWCfgEntry entries[2][FW_CFG_MAX_ENTRY];
FWCfgFiles *files;
uint16_t cur_entry;
uint32_t cur_offset;
Notifier machine_ready;
};
#define JPG_FILE 0
#define BMP_FILE 1
static char *read_splashfile(char *filename, size_t *file_sizep,
int *file_typep)
{
GError *err = NULL;
gboolean res;
gchar *content;
int file_type;
unsigned int filehead;
int bmp_bpp;
res = g_file_get_contents(filename, &content, file_sizep, &err);
if (res == FALSE) {
error_report("failed to read splash file '%s'", filename);
g_error_free(err);
return NULL;
}
/* check file size */
if (*file_sizep < 30) {
goto error;
}
/* check magic ID */
filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff;
if (filehead == 0xd8ff) {
file_type = JPG_FILE;
} else if (filehead == 0x4d42) {
file_type = BMP_FILE;
} else {
goto error;
}
/* check BMP bpp */
if (file_type == BMP_FILE) {
bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff;
if (bmp_bpp != 24) {
goto error;
}
}
/* return values */
*file_typep = file_type;
return content;
error:
error_report("splash file '%s' format not recognized; must be JPEG "
"or 24 bit BMP", filename);
g_free(content);
return NULL;
}
static void fw_cfg_bootsplash(FWCfgState *s)
{
int boot_splash_time = -1;
const char *boot_splash_filename = NULL;
char *p;
char *filename, *file_data;
size_t file_size;
int file_type;
const char *temp;
/* get user configuration */
QemuOptsList *plist = qemu_find_opts("boot-opts");
QemuOpts *opts = QTAILQ_FIRST(&plist->head);
if (opts != NULL) {
temp = qemu_opt_get(opts, "splash");
if (temp != NULL) {
boot_splash_filename = temp;
}
temp = qemu_opt_get(opts, "splash-time");
if (temp != NULL) {
p = (char *)temp;
boot_splash_time = strtol(p, (char **)&p, 10);
}
}
/* insert splash time if user configurated */
if (boot_splash_time >= 0) {
/* validate the input */
if (boot_splash_time > 0xffff) {
error_report("splash time is big than 65535, force it to 65535.");
boot_splash_time = 0xffff;
}
/* use little endian format */
qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff);
qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff);
fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2);
}
/* insert splash file if user configurated */
if (boot_splash_filename != NULL) {
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
if (filename == NULL) {
error_report("failed to find file '%s'.", boot_splash_filename);
return;
}
/* loading file data */
file_data = read_splashfile(filename, &file_size, &file_type);
if (file_data == NULL) {
g_free(filename);
return;
}
if (boot_splash_filedata != NULL) {
g_free(boot_splash_filedata);
}
boot_splash_filedata = (uint8_t *)file_data;
boot_splash_filedata_size = file_size;
/* insert data */
if (file_type == JPG_FILE) {
fw_cfg_add_file(s, "bootsplash.jpg",
boot_splash_filedata, boot_splash_filedata_size);
} else {
fw_cfg_add_file(s, "bootsplash.bmp",
boot_splash_filedata, boot_splash_filedata_size);
}
g_free(filename);
}
}
static void fw_cfg_reboot(FWCfgState *s)
{
int reboot_timeout = -1;
char *p;
const char *temp;
/* get user configuration */
QemuOptsList *plist = qemu_find_opts("boot-opts");
QemuOpts *opts = QTAILQ_FIRST(&plist->head);
if (opts != NULL) {
temp = qemu_opt_get(opts, "reboot-timeout");
if (temp != NULL) {
p = (char *)temp;
reboot_timeout = strtol(p, (char **)&p, 10);
}
}
/* validate the input */
if (reboot_timeout > 0xffff) {
error_report("reboot timeout is larger than 65535, force it to 65535.");
reboot_timeout = 0xffff;
}
fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4);
}
static void fw_cfg_write(FWCfgState *s, uint8_t value)
{
int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
trace_fw_cfg_write(s, value);
if (s->cur_entry & FW_CFG_WRITE_CHANNEL && e->callback &&
s->cur_offset < e->len) {
e->data[s->cur_offset++] = value;
if (s->cur_offset == e->len) {
e->callback(e->callback_opaque, e->data);
s->cur_offset = 0;
}
}
}
static int fw_cfg_select(FWCfgState *s, uint16_t key)
{
int ret;
s->cur_offset = 0;
if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) {
s->cur_entry = FW_CFG_INVALID;
ret = 0;
} else {
s->cur_entry = key;
ret = 1;
}
trace_fw_cfg_select(s, key, ret);
return ret;
}
static uint8_t fw_cfg_read(FWCfgState *s)
{
int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
uint8_t ret;
if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len)
ret = 0;
else
ret = e->data[s->cur_offset++];
trace_fw_cfg_read(s, ret);
return ret;
}
static uint64_t fw_cfg_data_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
}
static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
fw_cfg_select(opaque, (uint16_t)value);
}
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return is_write && size == 2;
}
static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
static void fw_cfg_comb_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
case 1:
fw_cfg_write(opaque, (uint8_t)value);
break;
case 2:
fw_cfg_select(opaque, (uint16_t)value);
break;
}
}
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 2);
}
static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
.write = fw_cfg_ctl_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.accepts = fw_cfg_ctl_mem_valid,
};
static const MemoryRegionOps fw_cfg_data_mem_ops = {
.read = fw_cfg_data_mem_read,
.write = fw_cfg_data_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static const MemoryRegionOps fw_cfg_comb_mem_ops = {
.read = fw_cfg_comb_read,
.write = fw_cfg_comb_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.accepts = fw_cfg_comb_valid,
};
static void fw_cfg_reset(DeviceState *d)
{
FWCfgState *s = DO_UPCAST(FWCfgState, busdev.qdev, d);
fw_cfg_select(s, 0);
}
/* Save restore 32 bit int as uint16_t
This is a Big hack, but it is how the old state did it.
Or we broke compatibility in the state, or we can't use struct tm
*/
static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size)
{
uint32_t *v = pv;
*v = qemu_get_be16(f);
return 0;
}
static void put_unused(QEMUFile *f, void *pv, size_t size)
{
fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
fprintf(stderr, "This functions shouldn't be called.\n");
}
static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
.name = "int32_as_uint16",
.get = get_uint32_as_uint16,
.put = put_unused,
};
#define VMSTATE_UINT16_HACK(_f, _s, _t) \
VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
static bool is_version_1(void *opaque, int version_id)
{
return version_id == 1;
}
static const VMStateDescription vmstate_fw_cfg = {
.name = "fw_cfg",
.version_id = 2,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
VMSTATE_UINT16(cur_entry, FWCfgState),
VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
VMSTATE_END_OF_LIST()
}
};
void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
{
int arch = !!(key & FW_CFG_ARCH_LOCAL);
key &= FW_CFG_ENTRY_MASK;
assert(key < FW_CFG_MAX_ENTRY && len < UINT32_MAX);
s->entries[arch][key].data = data;
s->entries[arch][key].len = (uint32_t)len;
}
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
{
size_t sz = strlen(value) + 1;
return fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
}
void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
{
uint16_t *copy;
copy = g_malloc(sizeof(value));
*copy = cpu_to_le16(value);
fw_cfg_add_bytes(s, key, copy, sizeof(value));
}
void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
{
uint32_t *copy;
copy = g_malloc(sizeof(value));
*copy = cpu_to_le32(value);
fw_cfg_add_bytes(s, key, copy, sizeof(value));
}
void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
{
uint64_t *copy;
copy = g_malloc(sizeof(value));
*copy = cpu_to_le64(value);
fw_cfg_add_bytes(s, key, copy, sizeof(value));
}
void fw_cfg_add_callback(FWCfgState *s, uint16_t key, FWCfgCallback callback,
void *callback_opaque, void *data, size_t len)
{
int arch = !!(key & FW_CFG_ARCH_LOCAL);
assert(key & FW_CFG_WRITE_CHANNEL);
key &= FW_CFG_ENTRY_MASK;
assert(key < FW_CFG_MAX_ENTRY && len <= UINT32_MAX);
s->entries[arch][key].data = data;
s->entries[arch][key].len = (uint32_t)len;
s->entries[arch][key].callback_opaque = callback_opaque;
s->entries[arch][key].callback = callback;
}
void fw_cfg_add_file(FWCfgState *s, const char *filename,
void *data, size_t len)
{
int i, index;
size_t dsize;
if (!s->files) {
dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * FW_CFG_FILE_SLOTS;
s->files = g_malloc0(dsize);
fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
}
index = be32_to_cpu(s->files->count);
assert(index < FW_CFG_FILE_SLOTS);
fw_cfg_add_bytes(s, FW_CFG_FILE_FIRST + index, data, len);
pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name),
filename);
for (i = 0; i < index; i++) {
if (strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
trace_fw_cfg_add_file_dupe(s, s->files->f[index].name);
return;
}
}
s->files->f[index].size = cpu_to_be32(len);
s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
s->files->count = cpu_to_be32(index+1);
}
static void fw_cfg_machine_ready(struct Notifier *n, void *data)
{
size_t len;
FWCfgState *s = container_of(n, FWCfgState, machine_ready);
char *bootindex = get_boot_devices_list(&len);
fw_cfg_add_file(s, "bootorder", (uint8_t*)bootindex, len);
}
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
hwaddr ctl_addr, hwaddr data_addr)
{
DeviceState *dev;
SysBusDevice *d;
FWCfgState *s;
dev = qdev_create(NULL, "fw_cfg");
qdev_prop_set_uint32(dev, "ctl_iobase", ctl_port);
qdev_prop_set_uint32(dev, "data_iobase", data_port);
qdev_init_nofail(dev);
d = SYS_BUS_DEVICE(dev);
s = DO_UPCAST(FWCfgState, busdev.qdev, dev);
if (ctl_addr) {
sysbus_mmio_map(d, 0, ctl_addr);
}
if (data_addr) {
sysbus_mmio_map(d, 1, data_addr);
}
fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
fw_cfg_bootsplash(s);
fw_cfg_reboot(s);
s->machine_ready.notify = fw_cfg_machine_ready;
qemu_add_machine_init_done_notifier(&s->machine_ready);
return s;
}
static int fw_cfg_init1(SysBusDevice *dev)
{
FWCfgState *s = FROM_SYSBUS(FWCfgState, dev);
memory_region_init_io(&s->ctl_iomem, &fw_cfg_ctl_mem_ops, s,
"fwcfg.ctl", FW_CFG_SIZE);
sysbus_init_mmio(dev, &s->ctl_iomem);
memory_region_init_io(&s->data_iomem, &fw_cfg_data_mem_ops, s,
"fwcfg.data", FW_CFG_DATA_SIZE);
sysbus_init_mmio(dev, &s->data_iomem);
/* In case ctl and data overlap: */
memory_region_init_io(&s->comb_iomem, &fw_cfg_comb_mem_ops, s,
"fwcfg", FW_CFG_SIZE);
if (s->ctl_iobase + 1 == s->data_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->comb_iomem);
} else {
if (s->ctl_iobase) {
sysbus_add_io(dev, s->ctl_iobase, &s->ctl_iomem);
}
if (s->data_iobase) {
sysbus_add_io(dev, s->data_iobase, &s->data_iomem);
}
}
return 0;
}
static Property fw_cfg_properties[] = {
DEFINE_PROP_HEX32("ctl_iobase", FWCfgState, ctl_iobase, -1),
DEFINE_PROP_HEX32("data_iobase", FWCfgState, data_iobase, -1),
DEFINE_PROP_END_OF_LIST(),
};
static void fw_cfg_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = fw_cfg_init1;
dc->no_user = 1;
dc->reset = fw_cfg_reset;
dc->vmsd = &vmstate_fw_cfg;
dc->props = fw_cfg_properties;
}
static const TypeInfo fw_cfg_info = {
.name = "fw_cfg",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(FWCfgState),
.class_init = fw_cfg_class_init,
};
static void fw_cfg_register_types(void)
{
type_register_static(&fw_cfg_info);
}
type_init(fw_cfg_register_types)

196
hw/nvram/mac_nvram.c Normal file
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@ -0,0 +1,196 @@
/*
* PowerMac NVRAM emulation
*
* Copyright (c) 2005-2007 Fabrice Bellard
* Copyright (c) 2007 Jocelyn Mayer
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/hw.h"
#include "hw/sparc/firmware_abi.h"
#include "sysemu/sysemu.h"
#include "hw/ppc/mac.h"
/* debug NVR */
//#define DEBUG_NVR
#ifdef DEBUG_NVR
#define NVR_DPRINTF(fmt, ...) \
do { printf("NVR: " fmt , ## __VA_ARGS__); } while (0)
#else
#define NVR_DPRINTF(fmt, ...)
#endif
#define DEF_SYSTEM_SIZE 0xc10
/* Direct access to NVRAM */
uint8_t macio_nvram_read(MacIONVRAMState *s, uint32_t addr)
{
uint32_t ret;
if (addr < s->size) {
ret = s->data[addr];
} else {
ret = -1;
}
NVR_DPRINTF("read addr %04" PRIx32 " val %" PRIx8 "\n", addr, ret);
return ret;
}
void macio_nvram_write(MacIONVRAMState *s, uint32_t addr, uint8_t val)
{
NVR_DPRINTF("write addr %04" PRIx32 " val %" PRIx8 "\n", addr, val);
if (addr < s->size) {
s->data[addr] = val;
}
}
/* macio style NVRAM device */
static void macio_nvram_writeb(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
MacIONVRAMState *s = opaque;
addr = (addr >> s->it_shift) & (s->size - 1);
s->data[addr] = value;
NVR_DPRINTF("writeb addr %04" PHYS_PRIx " val %" PRIx64 "\n", addr, value);
}
static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
unsigned size)
{
MacIONVRAMState *s = opaque;
uint32_t value;
addr = (addr >> s->it_shift) & (s->size - 1);
value = s->data[addr];
NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
return value;
}
static const MemoryRegionOps macio_nvram_ops = {
.read = macio_nvram_readb,
.write = macio_nvram_writeb,
.endianness = DEVICE_BIG_ENDIAN,
};
static const VMStateDescription vmstate_macio_nvram = {
.name = "macio_nvram",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_VBUFFER_UINT32(data, MacIONVRAMState, 0, NULL, 0, size),
VMSTATE_END_OF_LIST()
}
};
static void macio_nvram_reset(DeviceState *dev)
{
}
static void macio_nvram_realizefn(DeviceState *dev, Error **errp)
{
SysBusDevice *d = SYS_BUS_DEVICE(dev);
MacIONVRAMState *s = MACIO_NVRAM(dev);
s->data = g_malloc0(s->size);
memory_region_init_io(&s->mem, &macio_nvram_ops, s, "macio-nvram",
s->size << s->it_shift);
sysbus_init_mmio(d, &s->mem);
}
static void macio_nvram_unrealizefn(DeviceState *dev, Error **errp)
{
MacIONVRAMState *s = MACIO_NVRAM(dev);
g_free(s->data);
}
static Property macio_nvram_properties[] = {
DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0),
DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0),
DEFINE_PROP_END_OF_LIST()
};
static void macio_nvram_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = macio_nvram_realizefn;
dc->unrealize = macio_nvram_unrealizefn;
dc->reset = macio_nvram_reset;
dc->vmsd = &vmstate_macio_nvram;
dc->props = macio_nvram_properties;
}
static const TypeInfo macio_nvram_type_info = {
.name = TYPE_MACIO_NVRAM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MacIONVRAMState),
.class_init = macio_nvram_class_init,
};
static void macio_nvram_register_types(void)
{
type_register_static(&macio_nvram_type_info);
}
/* Set up a system OpenBIOS NVRAM partition */
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len)
{
unsigned int i;
uint32_t start = 0, end;
struct OpenBIOS_nvpart_v1 *part_header;
// OpenBIOS nvram variables
// Variable partition
part_header = (struct OpenBIOS_nvpart_v1 *)nvr->data;
part_header->signature = OPENBIOS_PART_SYSTEM;
pstrcpy(part_header->name, sizeof(part_header->name), "system");
end = start + sizeof(struct OpenBIOS_nvpart_v1);
for (i = 0; i < nb_prom_envs; i++)
end = OpenBIOS_set_var(nvr->data, end, prom_envs[i]);
// End marker
nvr->data[end++] = '\0';
end = start + ((end - start + 15) & ~15);
/* XXX: OpenBIOS is not able to grow up a partition. Leave some space for
new variables. */
if (end < DEF_SYSTEM_SIZE)
end = DEF_SYSTEM_SIZE;
OpenBIOS_finish_partition(part_header, end - start);
// free partition
start = end;
part_header = (struct OpenBIOS_nvpart_v1 *)&nvr->data[start];
part_header->signature = OPENBIOS_PART_FREE;
pstrcpy(part_header->name, sizeof(part_header->name), "free");
end = len;
OpenBIOS_finish_partition(part_header, end - start);
}
type_init(macio_nvram_register_types)