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https://github.com/Motorhead1991/qemu.git
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hw: move target-independent files to subdirectories
This patch tackles all files that are compiled once, moving them to subdirectories of hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
ce3b494cb5
commit
49ab747f66
227 changed files with 205 additions and 208 deletions
421
hw/dma/pl080.c
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421
hw/dma/pl080.c
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@ -0,0 +1,421 @@
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/*
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* Arm PrimeCell PL080/PL081 DMA controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/sysbus.h"
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#define PL080_MAX_CHANNELS 8
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#define PL080_CONF_E 0x1
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#define PL080_CONF_M1 0x2
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#define PL080_CONF_M2 0x4
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#define PL080_CCONF_H 0x40000
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#define PL080_CCONF_A 0x20000
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#define PL080_CCONF_L 0x10000
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#define PL080_CCONF_ITC 0x08000
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#define PL080_CCONF_IE 0x04000
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#define PL080_CCONF_E 0x00001
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#define PL080_CCTRL_I 0x80000000
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#define PL080_CCTRL_DI 0x08000000
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#define PL080_CCTRL_SI 0x04000000
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#define PL080_CCTRL_D 0x02000000
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#define PL080_CCTRL_S 0x01000000
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typedef struct {
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uint32_t src;
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uint32_t dest;
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uint32_t lli;
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uint32_t ctrl;
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uint32_t conf;
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} pl080_channel;
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint8_t tc_int;
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uint8_t tc_mask;
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uint8_t err_int;
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uint8_t err_mask;
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uint32_t conf;
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uint32_t sync;
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uint32_t req_single;
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uint32_t req_burst;
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pl080_channel chan[PL080_MAX_CHANNELS];
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int nchannels;
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/* Flag to avoid recursive DMA invocations. */
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int running;
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qemu_irq irq;
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} pl080_state;
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static const VMStateDescription vmstate_pl080_channel = {
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.name = "pl080_channel",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(src, pl080_channel),
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VMSTATE_UINT32(dest, pl080_channel),
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VMSTATE_UINT32(lli, pl080_channel),
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VMSTATE_UINT32(ctrl, pl080_channel),
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VMSTATE_UINT32(conf, pl080_channel),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pl080 = {
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.name = "pl080",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(tc_int, pl080_state),
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VMSTATE_UINT8(tc_mask, pl080_state),
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VMSTATE_UINT8(err_int, pl080_state),
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VMSTATE_UINT8(err_mask, pl080_state),
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VMSTATE_UINT32(conf, pl080_state),
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VMSTATE_UINT32(sync, pl080_state),
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VMSTATE_UINT32(req_single, pl080_state),
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VMSTATE_UINT32(req_burst, pl080_state),
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VMSTATE_UINT8(tc_int, pl080_state),
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VMSTATE_UINT8(tc_int, pl080_state),
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VMSTATE_UINT8(tc_int, pl080_state),
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VMSTATE_STRUCT_ARRAY(chan, pl080_state, PL080_MAX_CHANNELS,
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1, vmstate_pl080_channel, pl080_channel),
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VMSTATE_INT32(running, pl080_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static const unsigned char pl080_id[] =
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{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
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static const unsigned char pl081_id[] =
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{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
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static void pl080_update(pl080_state *s)
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{
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if ((s->tc_int & s->tc_mask)
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|| (s->err_int & s->err_mask))
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qemu_irq_raise(s->irq);
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else
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qemu_irq_lower(s->irq);
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}
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static void pl080_run(pl080_state *s)
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{
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int c;
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int flow;
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pl080_channel *ch;
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int swidth;
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int dwidth;
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int xsize;
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int n;
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int src_id;
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int dest_id;
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int size;
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uint8_t buff[4];
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uint32_t req;
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s->tc_mask = 0;
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for (c = 0; c < s->nchannels; c++) {
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if (s->chan[c].conf & PL080_CCONF_ITC)
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s->tc_mask |= 1 << c;
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if (s->chan[c].conf & PL080_CCONF_IE)
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s->err_mask |= 1 << c;
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}
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if ((s->conf & PL080_CONF_E) == 0)
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return;
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hw_error("DMA active\n");
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/* If we are already in the middle of a DMA operation then indicate that
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there may be new DMA requests and return immediately. */
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if (s->running) {
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s->running++;
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return;
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}
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s->running = 1;
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while (s->running) {
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for (c = 0; c < s->nchannels; c++) {
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ch = &s->chan[c];
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again:
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/* Test if thiws channel has any pending DMA requests. */
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if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
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!= PL080_CCONF_E)
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continue;
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flow = (ch->conf >> 11) & 7;
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if (flow >= 4) {
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hw_error(
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"pl080_run: Peripheral flow control not implemented\n");
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}
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src_id = (ch->conf >> 1) & 0x1f;
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dest_id = (ch->conf >> 6) & 0x1f;
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size = ch->ctrl & 0xfff;
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req = s->req_single | s->req_burst;
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switch (flow) {
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case 0:
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break;
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case 1:
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if ((req & (1u << dest_id)) == 0)
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size = 0;
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break;
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case 2:
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if ((req & (1u << src_id)) == 0)
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size = 0;
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break;
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case 3:
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if ((req & (1u << src_id)) == 0
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|| (req & (1u << dest_id)) == 0)
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size = 0;
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break;
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}
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if (!size)
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continue;
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/* Transfer one element. */
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/* ??? Should transfer multiple elements for a burst request. */
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/* ??? Unclear what the proper behavior is when source and
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destination widths are different. */
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swidth = 1 << ((ch->ctrl >> 18) & 7);
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dwidth = 1 << ((ch->ctrl >> 21) & 7);
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for (n = 0; n < dwidth; n+= swidth) {
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cpu_physical_memory_read(ch->src, buff + n, swidth);
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if (ch->ctrl & PL080_CCTRL_SI)
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ch->src += swidth;
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}
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xsize = (dwidth < swidth) ? swidth : dwidth;
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/* ??? This may pad the value incorrectly for dwidth < 32. */
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for (n = 0; n < xsize; n += dwidth) {
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cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
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if (ch->ctrl & PL080_CCTRL_DI)
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ch->dest += swidth;
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}
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size--;
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ch->ctrl = (ch->ctrl & 0xfffff000) | size;
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if (size == 0) {
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/* Transfer complete. */
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if (ch->lli) {
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ch->src = ldl_le_phys(ch->lli);
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ch->dest = ldl_le_phys(ch->lli + 4);
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ch->ctrl = ldl_le_phys(ch->lli + 12);
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ch->lli = ldl_le_phys(ch->lli + 8);
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} else {
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ch->conf &= ~PL080_CCONF_E;
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}
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if (ch->ctrl & PL080_CCTRL_I) {
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s->tc_int |= 1 << c;
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}
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}
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goto again;
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}
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if (--s->running)
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s->running = 1;
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}
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}
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static uint64_t pl080_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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pl080_state *s = (pl080_state *)opaque;
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uint32_t i;
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uint32_t mask;
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if (offset >= 0xfe0 && offset < 0x1000) {
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if (s->nchannels == 8) {
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return pl080_id[(offset - 0xfe0) >> 2];
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} else {
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return pl081_id[(offset - 0xfe0) >> 2];
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}
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}
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if (offset >= 0x100 && offset < 0x200) {
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i = (offset & 0xe0) >> 5;
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if (i >= s->nchannels)
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goto bad_offset;
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switch (offset >> 2) {
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case 0: /* SrcAddr */
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return s->chan[i].src;
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case 1: /* DestAddr */
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return s->chan[i].dest;
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case 2: /* LLI */
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return s->chan[i].lli;
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case 3: /* Control */
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return s->chan[i].ctrl;
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case 4: /* Configuration */
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return s->chan[i].conf;
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default:
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goto bad_offset;
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}
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}
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switch (offset >> 2) {
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case 0: /* IntStatus */
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return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
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case 1: /* IntTCStatus */
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return (s->tc_int & s->tc_mask);
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case 3: /* IntErrorStatus */
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return (s->err_int & s->err_mask);
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case 5: /* RawIntTCStatus */
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return s->tc_int;
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case 6: /* RawIntErrorStatus */
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return s->err_int;
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case 7: /* EnbldChns */
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mask = 0;
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for (i = 0; i < s->nchannels; i++) {
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if (s->chan[i].conf & PL080_CCONF_E)
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mask |= 1 << i;
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}
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return mask;
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case 8: /* SoftBReq */
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case 9: /* SoftSReq */
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case 10: /* SoftLBReq */
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case 11: /* SoftLSReq */
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/* ??? Implement these. */
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return 0;
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case 12: /* Configuration */
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return s->conf;
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case 13: /* Sync */
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return s->sync;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl080_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void pl080_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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pl080_state *s = (pl080_state *)opaque;
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int i;
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if (offset >= 0x100 && offset < 0x200) {
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i = (offset & 0xe0) >> 5;
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if (i >= s->nchannels)
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goto bad_offset;
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switch (offset >> 2) {
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case 0: /* SrcAddr */
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s->chan[i].src = value;
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break;
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case 1: /* DestAddr */
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s->chan[i].dest = value;
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break;
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case 2: /* LLI */
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s->chan[i].lli = value;
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break;
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case 3: /* Control */
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s->chan[i].ctrl = value;
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break;
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case 4: /* Configuration */
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s->chan[i].conf = value;
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pl080_run(s);
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break;
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}
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}
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switch (offset >> 2) {
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case 2: /* IntTCClear */
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s->tc_int &= ~value;
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break;
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case 4: /* IntErrorClear */
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s->err_int &= ~value;
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break;
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case 8: /* SoftBReq */
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case 9: /* SoftSReq */
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case 10: /* SoftLBReq */
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case 11: /* SoftLSReq */
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/* ??? Implement these. */
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qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
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break;
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case 12: /* Configuration */
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s->conf = value;
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if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
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qemu_log_mask(LOG_UNIMP,
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"pl080_write: Big-endian DMA not implemented\n");
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}
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pl080_run(s);
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break;
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case 13: /* Sync */
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s->sync = value;
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break;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl080_write: Bad offset %x\n", (int)offset);
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}
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pl080_update(s);
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}
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static const MemoryRegionOps pl080_ops = {
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.read = pl080_read,
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.write = pl080_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int pl08x_init(SysBusDevice *dev, int nchannels)
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{
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pl080_state *s = FROM_SYSBUS(pl080_state, dev);
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memory_region_init_io(&s->iomem, &pl080_ops, s, "pl080", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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s->nchannels = nchannels;
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return 0;
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}
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static int pl080_init(SysBusDevice *dev)
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{
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return pl08x_init(dev, 8);
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}
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static int pl081_init(SysBusDevice *dev)
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{
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return pl08x_init(dev, 2);
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}
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static void pl080_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = pl080_init;
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dc->no_user = 1;
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dc->vmsd = &vmstate_pl080;
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}
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static const TypeInfo pl080_info = {
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.name = "pl080",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(pl080_state),
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.class_init = pl080_class_init,
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};
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static void pl081_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = pl081_init;
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dc->no_user = 1;
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dc->vmsd = &vmstate_pl080;
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}
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static const TypeInfo pl081_info = {
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.name = "pl081",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(pl080_state),
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.class_init = pl081_class_init,
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};
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/* The PL080 and PL081 are the same except for the number of channels
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they implement (8 and 2 respectively). */
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static void pl080_register_types(void)
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{
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type_register_static(&pl080_info);
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type_register_static(&pl081_info);
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}
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type_init(pl080_register_types)
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