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target/arm: Improve masking in arm_hcr_el2_eff

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Update the {TGE,E2H} == '11' masking to ARMv8.6.
If EL2 is configured for aarch32, disable all of
the bits that are RES0 in aarch32 mode.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-03-05 16:09:17 +00:00 • committed by Peter Maydell
parent a6c2b33811
commit 4990e1d3c1
1 changed files with 27 additions and 4 deletions
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31
target/arm/helper.c
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@ -5196,14 +5196,37 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
* Since the v8.4 language applies to the entire register, and * Since the v8.4 language applies to the entire register, and
* appears to be backward compatible, use that. * appears to be backward compatible, use that.
*/ */
ret = 0; return 0;
} else if (ret & HCR_TGE) { }
/* These bits are up-to-date as of ARMv8.4. */
/*
* For a cpu that supports both aarch64 and aarch32, we can set bits
* in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
* Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
*/
if (!arm_el_is_aa64(env, 2)) {
uint64_t aa32_valid;
/*
* These bits are up-to-date as of ARMv8.6.
* For HCR, it's easiest to list just the 2 bits that are invalid.
* For HCR2, list those that are valid.
*/
aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
ret &= aa32_valid;
}
if (ret & HCR_TGE) {
/* These bits are up-to-date as of ARMv8.6. */
if (ret & HCR_E2H) { if (ret & HCR_E2H) {
ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
} else { } else {
ret |= HCR_FMO | HCR_IMO | HCR_AMO; ret |= HCR_FMO | HCR_IMO | HCR_AMO;
} }