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target-arm queue:

Browse source 
* hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
  * hw/arm/fsl-imx25: Fix a typo
  * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
  * hw/arm/sbsa-ref : allocate IRQs for SMMUv3
  * hw/char/bcm2835_aux: Allow less than 32-bit accesses
  * hw/arm/virt: Implement kvm-steal-time
  * target/arm: Make '-cpu max' have a 48-bit PA
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201008-1' into staging

target-arm queue:
 * hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
 * hw/arm/fsl-imx25: Fix a typo
 * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
 * hw/arm/sbsa-ref : allocate IRQs for SMMUv3
 * hw/char/bcm2835_aux: Allow less than 32-bit accesses
 * hw/arm/virt: Implement kvm-steal-time
 * target/arm: Make '-cpu max' have a 48-bit PA

# gpg: Signature made Thu 08 Oct 2020 21:40:31 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201008-1:
  target/arm: Make '-cpu max' have a 48-bit PA
  hw/arm/virt: Implement kvm-steal-time
  tests/qtest: Restore aarch64 arm-cpu-features test
  hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
  hw/arm/virt: Move post cpu realize check into its own function
  target/arm/kvm: Make uncalled stubs explicitly unreachable
  linux headers: sync to 5.9-rc7
  hw/char/bcm2835_aux: Allow less than 32-bit accesses
  hw/arm/sbsa-ref : allocate IRQs for SMMUv3
  hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
  hw/arm/fsl-imx25: Fix a typo
  hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-10-08 21:41:20 +01:00
commit 497d415d76
18 changed files with 304 additions and 72 deletions
Download patch file Download diff file Expand all files Collapse all files

3
hw/arm/sbsa-ref.c
View file

@ -133,6 +133,7 @@ static const int sbsa_ref_irqmap[] = {
[SBSA_SECURE_UART_MM] = 9,
[SBSA_AHCI] = 10,
[SBSA_EHCI] = 11,
[SBSA_SMMU] = 12, /* ... to 15 */
};
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
@ -525,7 +526,7 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(sms->gic, irq + 1));
qdev_get_gpio_in(sms->gic, irq + i));
}
}

111
hw/arm/virt.c
View file

@ -151,6 +151,7 @@ static const MemMapEntry base_memmap[] = {
[VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
[VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
[VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
@ -521,21 +522,12 @@ static void fdt_add_gic_node(VirtMachineState *vms)
static void fdt_add_pmu_nodes(const VirtMachineState *vms)
{
CPUState *cpu;
ARMCPU *armcpu;
ARMCPU *armcpu = ARM_CPU(first_cpu);
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
CPU_FOREACH(cpu) {
armcpu = ARM_CPU(cpu);
if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
return;
}
if (kvm_enabled()) {
if (kvm_irqchip_in_kernel()) {
kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
}
kvm_arm_pmu_init(cpu);
}
if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
return;
}
if (vms->gic_version == VIRT_GIC_VERSION_2) {
@ -544,7 +536,6 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
(1 << vms->smp_cpus) - 1);
}
armcpu = ARM_CPU(qemu_get_cpu(0));
qemu_fdt_add_subnode(vms->fdt, "/pmu");
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
const char compat[] = "arm,armv8-pmuv3";
@ -1672,6 +1663,72 @@ static void finalize_gic_version(VirtMachineState *vms)
}
}
/*
* virt_cpu_post_init() must be called after the CPUs have
* been realized and the GIC has been created.
*/
static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
MemoryRegion *sysmem)
{
bool aarch64, pmu, steal_time;
CPUState *cpu;
aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
steal_time = object_property_get_bool(OBJECT(first_cpu),
"kvm-steal-time", NULL);
if (kvm_enabled()) {
hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
if (steal_time) {
MemoryRegion *pvtime = g_new(MemoryRegion, 1);
hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
/* The memory region size must be a multiple of host page size. */
pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
if (pvtime_size > pvtime_reg_size) {
error_report("pvtime requires a %" HWADDR_PRId
" byte memory region for %d CPUs,"
" but only %" HWADDR_PRId " has been reserved",
pvtime_size, max_cpus, pvtime_reg_size);
exit(1);
}
memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
}
CPU_FOREACH(cpu) {
if (pmu) {
assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
if (kvm_irqchip_in_kernel()) {
kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
}
kvm_arm_pmu_init(cpu);
}
if (steal_time) {
kvm_arm_pvtime_init(cpu, pvtime_reg_base +
cpu->cpu_index * PVTIME_SIZE_PER_CPU);
}
}
} else {
if (aarch64 && vms->highmem) {
int requested_pa_size = 64 - clz64(vms->highest_gpa);
int pamax = arm_pamax(ARM_CPU(first_cpu));
if (pamax < requested_pa_size) {
error_report("VCPU supports less PA bits (%d) than "
"requested by the memory map (%d)",
pamax, requested_pa_size);
exit(1);
}
}
}
}
static void machvirt_init(MachineState *machine)
{
VirtMachineState *vms = VIRT_MACHINE(machine);
@ -1826,6 +1883,11 @@ static void machvirt_init(MachineState *machine)
object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
}
if (vmc->no_kvm_steal_time &&
object_property_find(cpuobj, "kvm-steal-time")) {
object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
}
if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
object_property_set_bool(cpuobj, "pmu", false, NULL);
}
@ -1886,22 +1948,6 @@ static void machvirt_init(MachineState *machine)
fdt_add_timer_nodes(vms);
fdt_add_cpu_nodes(vms);
if (!kvm_enabled()) {
ARMCPU *cpu = ARM_CPU(first_cpu);
bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
if (aarch64 && vms->highmem) {
int requested_pa_size, pamax = arm_pamax(cpu);
requested_pa_size = 64 - clz64(vms->highest_gpa);
if (pamax < requested_pa_size) {
error_report("VCPU supports less PA bits (%d) than requested "
"by the memory map (%d)", pamax, requested_pa_size);
exit(1);
}
}
}
memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
machine->ram);
if (machine->device_memory) {
@ -1913,6 +1959,8 @@ static void machvirt_init(MachineState *machine)
create_gic(vms);
virt_cpu_post_init(vms, possible_cpus->len, sysmem);
fdt_add_pmu_nodes(vms);
create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
@ -2553,8 +2601,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
static void virt_machine_5_1_options(MachineClass *mc)
{
VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
virt_machine_5_2_options(mc);
compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
vmc->no_kvm_steal_time = true;
}
DEFINE_VIRT_MACHINE(5, 1)

4
hw/char/bcm2835_aux.c
View file

@ -249,7 +249,9 @@ static const MemoryRegionOps bcm2835_aux_ops = {
.read = bcm2835_aux_read,
.write = bcm2835_aux_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.min_access_size = 4,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
};

12
hw/ssi/npcm7xx_fiu.c
View file

@ -103,7 +103,8 @@ enum NPCM7xxFIURegister {
* Returns the index of flash in the fiu->flash array. This corresponds to the
* chip select ID of the flash.
*/
static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu,
NPCM7xxFIUFlash *flash)
{
int index = flash - fiu->flash;
@ -113,20 +114,19 @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
}
/* Assert the chip select specified in the UMA Control/Status Register. */
static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id)
{
trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
if (cs_id < s->cs_count) {
qemu_irq_lower(s->cs_lines[cs_id]);
s->active_cs = cs_id;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: UMA to CS%d; this module has only %d chip selects",
DEVICE(s)->canonical_path, cs_id, s->cs_count);
cs_id = -1;
s->active_cs = -1;
}
s->active_cs = cs_id;
}
/* Deassert the currently active chip select. */
@ -206,7 +206,7 @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
NPCM7xxFIUFlash *f = opaque;
NPCM7xxFIUState *fiu = f->fiu;
uint32_t dwr_cfg;
int cs_id;
unsigned cs_id;
int i;
if (fiu->active_cs != -1) {

2
hw/ssi/trace-events
View file

@ -19,4 +19,4 @@ npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64