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target/i386: Rework sse_op_table6/7
Add a flags field each row in sse_op_table6 and sse_op_table7. Initially this is only used as a replacement for the magic SSE41_SPECIAL pointer. The other flags are mostly relevant for the AVX implementation but can be applied to SSE as well. Signed-off-by: Paul Brook <paul@nowt.org> Message-Id: <20220424220204.2493824-6-paul@nowt.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paul Brook
Paolo Bonzini
parent
f2dbc28947
commit
491f0f1962
1 changed files with 131 additions and 99 deletions
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@ -2976,7 +2976,6 @@ static const struct SSEOpHelper_table1 sse_op_table1[256] = {
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#undef SSE_SPECIAL
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#undef SSE_SPECIAL
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#define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
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#define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
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#define SSE_SPECIAL_FN ((void *)1)
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static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
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static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
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[0 + 2] = MMX_OP2(psrlw),
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[0 + 2] = MMX_OP2(psrlw),
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@ -3060,113 +3059,134 @@ static const SSEFunc_0_epp sse_op_table5[256] = {
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[0xbf] = gen_helper_pavgb_mmx /* pavgusb */
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[0xbf] = gen_helper_pavgb_mmx /* pavgusb */
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};
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};
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struct SSEOpHelper_epp {
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struct SSEOpHelper_table6 {
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SSEFunc_0_epp op[2];
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SSEFunc_0_epp op[2];
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uint32_t ext_mask;
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uint32_t ext_mask;
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int flags;
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};
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};
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struct SSEOpHelper_eppi {
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struct SSEOpHelper_table7 {
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SSEFunc_0_eppi op[2];
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SSEFunc_0_eppi op[2];
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uint32_t ext_mask;
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uint32_t ext_mask;
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int flags;
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};
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};
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#define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
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#define gen_helper_special_xmm NULL
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#define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
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#define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
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#define SSE41_SPECIAL { { NULL, SSE_SPECIAL_FN }, CPUID_EXT_SSE41 }
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#define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
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CPUID_EXT_PCLMULQDQ }
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#define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
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static const struct SSEOpHelper_epp sse_op_table6[256] = {
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#define OP(name, op, flags, ext, mmx_name) \
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[0x00] = SSSE3_OP(pshufb),
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{{mmx_name, gen_helper_ ## name ## _xmm}, CPUID_EXT_ ## ext, flags}
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[0x01] = SSSE3_OP(phaddw),
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#define BINARY_OP_MMX(name, ext) \
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[0x02] = SSSE3_OP(phaddd),
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OP(name, op1, SSE_OPF_MMX, ext, gen_helper_ ## name ## _mmx)
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[0x03] = SSSE3_OP(phaddsw),
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#define BINARY_OP(name, ext, flags) \
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[0x04] = SSSE3_OP(pmaddubsw),
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OP(name, op1, flags, ext, NULL)
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[0x05] = SSSE3_OP(phsubw),
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#define UNARY_OP_MMX(name, ext) \
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[0x06] = SSSE3_OP(phsubd),
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OP(name, op1, SSE_OPF_MMX, ext, gen_helper_ ## name ## _mmx)
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[0x07] = SSSE3_OP(phsubsw),
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#define UNARY_OP(name, ext, flags) \
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[0x08] = SSSE3_OP(psignb),
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OP(name, op1, flags, ext, NULL)
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[0x09] = SSSE3_OP(psignw),
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#define BLENDV_OP(name, ext, flags) OP(name, op1, 0, ext, NULL)
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[0x0a] = SSSE3_OP(psignd),
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#define CMP_OP(name, ext) OP(name, op1, SSE_OPF_CMP, ext, NULL)
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[0x0b] = SSSE3_OP(pmulhrsw),
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#define SPECIAL_OP(ext) OP(special, op1, SSE_OPF_SPECIAL, ext, NULL)
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[0x10] = SSE41_OP(pblendvb),
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[0x14] = SSE41_OP(blendvps),
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/* prefix [66] 0f 38 */
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[0x15] = SSE41_OP(blendvpd),
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static const struct SSEOpHelper_table6 sse_op_table6[256] = {
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[0x17] = SSE41_OP(ptest),
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[0x00] = BINARY_OP_MMX(pshufb, SSSE3),
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[0x1c] = SSSE3_OP(pabsb),
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[0x01] = BINARY_OP_MMX(phaddw, SSSE3),
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[0x1d] = SSSE3_OP(pabsw),
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[0x02] = BINARY_OP_MMX(phaddd, SSSE3),
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[0x1e] = SSSE3_OP(pabsd),
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[0x03] = BINARY_OP_MMX(phaddsw, SSSE3),
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[0x20] = SSE41_OP(pmovsxbw),
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[0x04] = BINARY_OP_MMX(pmaddubsw, SSSE3),
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[0x21] = SSE41_OP(pmovsxbd),
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[0x05] = BINARY_OP_MMX(phsubw, SSSE3),
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[0x22] = SSE41_OP(pmovsxbq),
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[0x06] = BINARY_OP_MMX(phsubd, SSSE3),
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[0x23] = SSE41_OP(pmovsxwd),
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[0x07] = BINARY_OP_MMX(phsubsw, SSSE3),
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[0x24] = SSE41_OP(pmovsxwq),
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[0x08] = BINARY_OP_MMX(psignb, SSSE3),
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[0x25] = SSE41_OP(pmovsxdq),
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[0x09] = BINARY_OP_MMX(psignw, SSSE3),
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[0x28] = SSE41_OP(pmuldq),
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[0x0a] = BINARY_OP_MMX(psignd, SSSE3),
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[0x29] = SSE41_OP(pcmpeqq),
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[0x0b] = BINARY_OP_MMX(pmulhrsw, SSSE3),
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[0x2a] = SSE41_SPECIAL, /* movntqda */
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[0x10] = BLENDV_OP(pblendvb, SSE41, SSE_OPF_MMX),
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[0x2b] = SSE41_OP(packusdw),
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[0x14] = BLENDV_OP(blendvps, SSE41, 0),
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[0x30] = SSE41_OP(pmovzxbw),
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[0x15] = BLENDV_OP(blendvpd, SSE41, 0),
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[0x31] = SSE41_OP(pmovzxbd),
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[0x17] = CMP_OP(ptest, SSE41),
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[0x32] = SSE41_OP(pmovzxbq),
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[0x1c] = UNARY_OP_MMX(pabsb, SSSE3),
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[0x33] = SSE41_OP(pmovzxwd),
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[0x1d] = UNARY_OP_MMX(pabsw, SSSE3),
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[0x34] = SSE41_OP(pmovzxwq),
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[0x1e] = UNARY_OP_MMX(pabsd, SSSE3),
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[0x35] = SSE41_OP(pmovzxdq),
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[0x20] = UNARY_OP(pmovsxbw, SSE41, SSE_OPF_MMX),
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[0x37] = SSE42_OP(pcmpgtq),
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[0x21] = UNARY_OP(pmovsxbd, SSE41, SSE_OPF_MMX),
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[0x38] = SSE41_OP(pminsb),
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[0x22] = UNARY_OP(pmovsxbq, SSE41, SSE_OPF_MMX),
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[0x39] = SSE41_OP(pminsd),
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[0x23] = UNARY_OP(pmovsxwd, SSE41, SSE_OPF_MMX),
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[0x3a] = SSE41_OP(pminuw),
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[0x24] = UNARY_OP(pmovsxwq, SSE41, SSE_OPF_MMX),
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[0x3b] = SSE41_OP(pminud),
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[0x25] = UNARY_OP(pmovsxdq, SSE41, SSE_OPF_MMX),
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[0x3c] = SSE41_OP(pmaxsb),
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[0x28] = BINARY_OP(pmuldq, SSE41, SSE_OPF_MMX),
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[0x3d] = SSE41_OP(pmaxsd),
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[0x29] = BINARY_OP(pcmpeqq, SSE41, SSE_OPF_MMX),
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[0x3e] = SSE41_OP(pmaxuw),
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[0x2a] = SPECIAL_OP(SSE41), /* movntqda */
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[0x3f] = SSE41_OP(pmaxud),
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[0x2b] = BINARY_OP(packusdw, SSE41, SSE_OPF_MMX),
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[0x40] = SSE41_OP(pmulld),
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[0x30] = UNARY_OP(pmovzxbw, SSE41, SSE_OPF_MMX),
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[0x41] = SSE41_OP(phminposuw),
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[0x31] = UNARY_OP(pmovzxbd, SSE41, SSE_OPF_MMX),
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[0xdb] = AESNI_OP(aesimc),
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[0x32] = UNARY_OP(pmovzxbq, SSE41, SSE_OPF_MMX),
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[0xdc] = AESNI_OP(aesenc),
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[0x33] = UNARY_OP(pmovzxwd, SSE41, SSE_OPF_MMX),
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[0xdd] = AESNI_OP(aesenclast),
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[0x34] = UNARY_OP(pmovzxwq, SSE41, SSE_OPF_MMX),
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[0xde] = AESNI_OP(aesdec),
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[0x35] = UNARY_OP(pmovzxdq, SSE41, SSE_OPF_MMX),
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[0xdf] = AESNI_OP(aesdeclast),
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[0x37] = BINARY_OP(pcmpgtq, SSE41, SSE_OPF_MMX),
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[0x38] = BINARY_OP(pminsb, SSE41, SSE_OPF_MMX),
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[0x39] = BINARY_OP(pminsd, SSE41, SSE_OPF_MMX),
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[0x3a] = BINARY_OP(pminuw, SSE41, SSE_OPF_MMX),
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[0x3b] = BINARY_OP(pminud, SSE41, SSE_OPF_MMX),
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[0x3c] = BINARY_OP(pmaxsb, SSE41, SSE_OPF_MMX),
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[0x3d] = BINARY_OP(pmaxsd, SSE41, SSE_OPF_MMX),
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[0x3e] = BINARY_OP(pmaxuw, SSE41, SSE_OPF_MMX),
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[0x3f] = BINARY_OP(pmaxud, SSE41, SSE_OPF_MMX),
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[0x40] = BINARY_OP(pmulld, SSE41, SSE_OPF_MMX),
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[0x41] = UNARY_OP(phminposuw, SSE41, 0),
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[0xdb] = UNARY_OP(aesimc, AES, 0),
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[0xdc] = BINARY_OP(aesenc, AES, 0),
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[0xdd] = BINARY_OP(aesenclast, AES, 0),
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[0xde] = BINARY_OP(aesdec, AES, 0),
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[0xdf] = BINARY_OP(aesdeclast, AES, 0),
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};
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};
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static const struct SSEOpHelper_eppi sse_op_table7[256] = {
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/* prefix [66] 0f 3a */
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[0x08] = SSE41_OP(roundps),
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static const struct SSEOpHelper_table7 sse_op_table7[256] = {
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[0x09] = SSE41_OP(roundpd),
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[0x08] = UNARY_OP(roundps, SSE41, 0),
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[0x0a] = SSE41_OP(roundss),
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[0x09] = UNARY_OP(roundpd, SSE41, 0),
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[0x0b] = SSE41_OP(roundsd),
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[0x0a] = UNARY_OP(roundss, SSE41, SSE_OPF_SCALAR),
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[0x0c] = SSE41_OP(blendps),
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[0x0b] = UNARY_OP(roundsd, SSE41, SSE_OPF_SCALAR),
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[0x0d] = SSE41_OP(blendpd),
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[0x0c] = BINARY_OP(blendps, SSE41, 0),
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[0x0e] = SSE41_OP(pblendw),
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[0x0d] = BINARY_OP(blendpd, SSE41, 0),
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[0x0f] = SSSE3_OP(palignr),
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[0x0e] = BINARY_OP(pblendw, SSE41, SSE_OPF_MMX),
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[0x14] = SSE41_SPECIAL, /* pextrb */
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[0x0f] = BINARY_OP_MMX(palignr, SSSE3),
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[0x15] = SSE41_SPECIAL, /* pextrw */
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[0x14] = SPECIAL_OP(SSE41), /* pextrb */
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[0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
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[0x15] = SPECIAL_OP(SSE41), /* pextrw */
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[0x17] = SSE41_SPECIAL, /* extractps */
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[0x16] = SPECIAL_OP(SSE41), /* pextrd/pextrq */
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[0x20] = SSE41_SPECIAL, /* pinsrb */
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[0x17] = SPECIAL_OP(SSE41), /* extractps */
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[0x21] = SSE41_SPECIAL, /* insertps */
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[0x20] = SPECIAL_OP(SSE41), /* pinsrb */
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[0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
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[0x21] = SPECIAL_OP(SSE41), /* insertps */
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[0x40] = SSE41_OP(dpps),
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[0x22] = SPECIAL_OP(SSE41), /* pinsrd/pinsrq */
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[0x41] = SSE41_OP(dppd),
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[0x40] = BINARY_OP(dpps, SSE41, 0),
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[0x42] = SSE41_OP(mpsadbw),
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[0x41] = BINARY_OP(dppd, SSE41, 0),
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[0x44] = PCLMULQDQ_OP(pclmulqdq),
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[0x42] = BINARY_OP(mpsadbw, SSE41, SSE_OPF_MMX),
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[0x60] = SSE42_OP(pcmpestrm),
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[0x44] = BINARY_OP(pclmulqdq, PCLMULQDQ, 0),
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[0x61] = SSE42_OP(pcmpestri),
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[0x60] = CMP_OP(pcmpestrm, SSE42),
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[0x62] = SSE42_OP(pcmpistrm),
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[0x61] = CMP_OP(pcmpestri, SSE42),
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[0x63] = SSE42_OP(pcmpistri),
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[0x62] = CMP_OP(pcmpistrm, SSE42),
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[0xdf] = AESNI_OP(aeskeygenassist),
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[0x63] = CMP_OP(pcmpistri, SSE42),
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[0xdf] = UNARY_OP(aeskeygenassist, AES, 0),
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};
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};
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#undef OP
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#undef BINARY_OP_MMX
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#undef BINARY_OP
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#undef UNARY_OP_MMX
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#undef UNARY_OP
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#undef BLENDV_OP
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#undef SPECIAL_OP
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static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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target_ulong pc_start)
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target_ulong pc_start)
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{
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{
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int b1, op1_offset, op2_offset, is_xmm, val;
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int b1, op1_offset, op2_offset, is_xmm, val;
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int modrm, mod, rm, reg;
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int modrm, mod, rm, reg;
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int sse_op_flags;
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int sse_op_flags;
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const struct SSEOpHelper_table6 *op6;
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const struct SSEOpHelper_table7 *op7;
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SSEFunc_0_epp sse_fn_epp;
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SSEFunc_0_epp sse_fn_epp;
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SSEFunc_0_eppi sse_fn_eppi;
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SSEFunc_0_ppi sse_fn_ppi;
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SSEFunc_0_ppi sse_fn_ppi;
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SSEFunc_0_eppt sse_fn_eppt;
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SSEFunc_0_eppt sse_fn_eppt;
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MemOp ot;
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MemOp ot;
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@ -3821,12 +3841,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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mod = (modrm >> 6) & 3;
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mod = (modrm >> 6) & 3;
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assert(b1 < 2);
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assert(b1 < 2);
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sse_fn_epp = sse_op_table6[b].op[b1];
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op6 = &sse_op_table6[b];
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if (!sse_fn_epp) {
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if (op6->ext_mask == 0) {
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goto unknown_op;
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goto unknown_op;
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}
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}
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if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
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if (!(s->cpuid_ext_features & op6->ext_mask)) {
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goto illegal_op;
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goto illegal_op;
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}
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if (b1) {
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if (b1) {
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op1_offset = ZMM_OFFSET(reg);
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op1_offset = ZMM_OFFSET(reg);
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@ -3863,6 +3884,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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}
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}
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}
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}
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} else {
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} else {
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if ((op6->flags & SSE_OPF_MMX) == 0) {
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goto unknown_op;
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}
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op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
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op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
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if (mod == 3) {
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if (mod == 3) {
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op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
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op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
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@ -3872,13 +3896,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_ldq_env_A0(s, op2_offset);
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gen_ldq_env_A0(s, op2_offset);
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}
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}
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}
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}
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if (sse_fn_epp == SSE_SPECIAL_FN) {
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if (!op6->op[b1]) {
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goto unknown_op;
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goto illegal_op;
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}
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}
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tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
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tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
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tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
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sse_fn_epp(cpu_env, s->ptr0, s->ptr1);
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op6->op[b1](cpu_env, s->ptr0, s->ptr1);
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if (b == 0x17) {
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if (b == 0x17) {
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set_cc_op(s, CC_OP_EFLAGS);
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set_cc_op(s, CC_OP_EFLAGS);
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@ -4249,16 +4273,21 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
||||||
mod = (modrm >> 6) & 3;
|
mod = (modrm >> 6) & 3;
|
||||||
|
|
||||||
assert(b1 < 2);
|
assert(b1 < 2);
|
||||||
sse_fn_eppi = sse_op_table7[b].op[b1];
|
op7 = &sse_op_table7[b];
|
||||||
if (!sse_fn_eppi) {
|
if (op7->ext_mask == 0) {
|
||||||
goto unknown_op;
|
goto unknown_op;
|
||||||
}
|
}
|
||||||
if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
|
if (!(s->cpuid_ext_features & op7->ext_mask)) {
|
||||||
goto illegal_op;
|
goto illegal_op;
|
||||||
|
}
|
||||||
|
|
||||||
s->rip_offset = 1;
|
s->rip_offset = 1;
|
||||||
|
|
||||||
if (sse_fn_eppi == SSE_SPECIAL_FN) {
|
if (op7->flags & SSE_OPF_SPECIAL) {
|
||||||
|
/* None of the "special" ops are valid on mmx registers */
|
||||||
|
if (b1 == 0) {
|
||||||
|
goto illegal_op;
|
||||||
|
}
|
||||||
ot = mo_64_32(s->dflag);
|
ot = mo_64_32(s->dflag);
|
||||||
rm = (modrm & 7) | REX_B(s);
|
rm = (modrm & 7) | REX_B(s);
|
||||||
if (mod != 3)
|
if (mod != 3)
|
||||||
|
|
@ -4403,6 +4432,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
||||||
gen_ldo_env_A0(s, op2_offset);
|
gen_ldo_env_A0(s, op2_offset);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
|
if ((op7->flags & SSE_OPF_MMX) == 0) {
|
||||||
|
goto illegal_op;
|
||||||
|
}
|
||||||
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
|
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
|
||||||
if (mod == 3) {
|
if (mod == 3) {
|
||||||
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
|
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
|
||||||
|
|
@ -4425,7 +4457,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
|
||||||
|
|
||||||
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
|
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
|
||||||
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
|
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
|
||||||
sse_fn_eppi(cpu_env, s->ptr0, s->ptr1, tcg_const_i32(val));
|
op7->op[b1](cpu_env, s->ptr0, s->ptr1, tcg_const_i32(val));
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 0x33a:
|
case 0x33a:
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue