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hw/misc/pll: Do not expose as user-creatable

Browse source 
All these devices are part of SoC components and can not
be created manually.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20250325224310.8785-9-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-03-25 23:21:17 +01:00
parent 2542d5cf47
commit 490aaae935
3 changed files with 18 additions and 0 deletions
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8
hw/misc/bcm2835_cprman.c
View file

@ -137,6 +137,8 @@ static void pll_class_init(ObjectClass *klass, void *data)
device_class_set_legacy_reset(dc, pll_reset); device_class_set_legacy_reset(dc, pll_reset);
dc->vmsd = &pll_vmstate; dc->vmsd = &pll_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
} }
static const TypeInfo cprman_pll_info = { static const TypeInfo cprman_pll_info = {
@ -241,6 +243,8 @@ static void pll_channel_class_init(ObjectClass *klass, void *data)
device_class_set_legacy_reset(dc, pll_channel_reset); device_class_set_legacy_reset(dc, pll_channel_reset);
dc->vmsd = &pll_channel_vmstate; dc->vmsd = &pll_channel_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
} }
static const TypeInfo cprman_pll_channel_info = { static const TypeInfo cprman_pll_channel_info = {
@ -362,6 +366,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data)
device_class_set_legacy_reset(dc, clock_mux_reset); device_class_set_legacy_reset(dc, clock_mux_reset);
dc->vmsd = &clock_mux_vmstate; dc->vmsd = &clock_mux_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
} }
static const TypeInfo cprman_clock_mux_info = { static const TypeInfo cprman_clock_mux_info = {
@ -416,6 +422,8 @@ static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &dsi0hsck_mux_vmstate; dc->vmsd = &dsi0hsck_mux_vmstate;
/* Reason: Part of BCM2835CprmanState component */
dc->user_creatable = false;
} }
static const TypeInfo cprman_dsi0hsck_mux_info = { static const TypeInfo cprman_dsi0hsck_mux_info = {

6
hw/misc/npcm_clk.c
View file

@ -1108,6 +1108,8 @@ static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
dc->desc = "NPCM7xx Clock PLL Module"; dc->desc = "NPCM7xx Clock PLL Module";
dc->vmsd = &vmstate_npcm7xx_clk_pll; dc->vmsd = &vmstate_npcm7xx_clk_pll;
/* Reason: Part of NPCMCLKState component */
dc->user_creatable = false;
} }
static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data) static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
@ -1116,6 +1118,8 @@ static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
dc->desc = "NPCM7xx Clock SEL Module"; dc->desc = "NPCM7xx Clock SEL Module";
dc->vmsd = &vmstate_npcm7xx_clk_sel; dc->vmsd = &vmstate_npcm7xx_clk_sel;
/* Reason: Part of NPCMCLKState component */
dc->user_creatable = false;
} }
static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data) static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
@ -1124,6 +1128,8 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
dc->desc = "NPCM7xx Clock Divider Module"; dc->desc = "NPCM7xx Clock Divider Module";
dc->vmsd = &vmstate_npcm7xx_clk_divider; dc->vmsd = &vmstate_npcm7xx_clk_divider;
/* Reason: Part of NPCMCLKState component */
dc->user_creatable = false;
} }
static void npcm_clk_class_init(ObjectClass *klass, void *data) static void npcm_clk_class_init(ObjectClass *klass, void *data)

4
hw/misc/stm32l4x5_rcc.c
View file

@ -150,6 +150,8 @@ static void clock_mux_class_init(ObjectClass *klass, void *data)
rc->phases.hold = clock_mux_reset_hold; rc->phases.hold = clock_mux_reset_hold;
rc->phases.exit = clock_mux_reset_exit; rc->phases.exit = clock_mux_reset_exit;
dc->vmsd = &clock_mux_vmstate; dc->vmsd = &clock_mux_vmstate;
/* Reason: Part of Stm32l4x5RccState component */
dc->user_creatable = false;
} }
static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled) static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled)
@ -302,6 +304,8 @@ static void pll_class_init(ObjectClass *klass, void *data)
rc->phases.hold = pll_reset_hold; rc->phases.hold = pll_reset_hold;
rc->phases.exit = pll_reset_exit; rc->phases.exit = pll_reset_exit;
dc->vmsd = &pll_vmstate; dc->vmsd = &pll_vmstate;
/* Reason: Part of Stm32l4x5RccState component */
dc->user_creatable = false;
} }
static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier) static void pll_set_vco_multiplier(RccPllState *pll, uint32_t vco_multiplier)