mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 17:23:56 -06:00
tcg: Remove INDEX_op_ext{8,16,32}*
Use the fully general extract opcodes instead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
2225fa242c
commit
48e8de684a
27 changed files with 135 additions and 823 deletions
|
@ -80,8 +80,6 @@ extern bool use_mips32r2_instructions;
|
|||
|
||||
/* optional instructions detected at runtime */
|
||||
#define TCG_TARGET_HAS_extract2_i32 0
|
||||
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_ctz_i32 0
|
||||
|
@ -93,23 +91,12 @@ extern bool use_mips32r2_instructions;
|
|||
#define TCG_TARGET_HAS_bswap32_i64 1
|
||||
#define TCG_TARGET_HAS_bswap64_i64 1
|
||||
#define TCG_TARGET_HAS_extract2_i64 0
|
||||
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions
|
||||
#define TCG_TARGET_HAS_ctz_i64 0
|
||||
#define TCG_TARGET_HAS_ctpop_i64 0
|
||||
#endif
|
||||
|
||||
/* optional instructions automatically implemented */
|
||||
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
|
||||
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
|
||||
|
||||
#if TCG_TARGET_REG_BITS == 64
|
||||
#define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
|
||||
#define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
|
||||
#endif
|
||||
|
||||
#define TCG_TARGET_HAS_qemu_ldst_i128 0
|
||||
#define TCG_TARGET_HAS_tst 0
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue