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hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()

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Move all the static initializion of the device to an init() function,
leaving only the dynamic initialization to be done during realize.

With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
init(), and realize() will increment s->cap with the extra caps.

This will allow callers to add IOMMU capabilities before the
realization.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-11-06 10:34:01 -03:00 • committed by Alistair Francis
parent 0d0141fadc
commit 4876e6f7b5
1 changed files with 39 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

71
hw/riscv/riscv-iommu.c
View file

@ -2130,11 +2130,48 @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
} }
}; };
static void riscv_iommu_instance_init(Object *obj)
{
RISCVIOMMUState *s = RISCV_IOMMU(obj);
/* Enable translation debug interface */
s->cap = RISCV_IOMMU_CAP_DBG;
/* Report QEMU target physical address space limits */
s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
TARGET_PHYS_ADDR_SPACE_BITS);
/* TODO: method to report supported PID bits */
s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
s->cap |= RISCV_IOMMU_CAP_PD8;
/* register storage */
s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
/* Mark all registers read-only */
memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
/* Device translation context cache */
s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
riscv_iommu_ctx_equal,
g_free, NULL);
s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
riscv_iommu_iot_equal,
g_free, NULL);
s->iommus.le_next = NULL;
s->iommus.le_prev = NULL;
QLIST_INIT(&s->spaces);
}
static void riscv_iommu_realize(DeviceState *dev, Error **errp) static void riscv_iommu_realize(DeviceState *dev, Error **errp)
{ {
RISCVIOMMUState *s = RISCV_IOMMU(dev); RISCVIOMMUState *s = RISCV_IOMMU(dev);
s->cap = s->version & RISCV_IOMMU_CAP_VERSION; s->cap |= s->version & RISCV_IOMMU_CAP_VERSION;
if (s->enable_msi) { if (s->enable_msi) {
s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF; s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;
} }
@ -2149,29 +2186,11 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 | s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4; RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
} }
/* Enable translation debug interface */
s->cap |= RISCV_IOMMU_CAP_DBG;
/* Report QEMU target physical address space limits */
s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
TARGET_PHYS_ADDR_SPACE_BITS);
/* TODO: method to report supported PID bits */
s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
s->cap |= RISCV_IOMMU_CAP_PD8;
/* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */ /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */
s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ? s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE); RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE);
/* register storage */
s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
/* Mark all registers read-only */
memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
/* /*
* Register complete MMIO space, including MSI/PBA registers. * Register complete MMIO space, including MSI/PBA registers.
* Note, PCIDevice implementation will add overlapping MR for MSI/PBA, * Note, PCIDevice implementation will add overlapping MR for MSI/PBA,
@ -2229,19 +2248,6 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s, memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s,
"riscv-iommu-trap", ~0ULL); "riscv-iommu-trap", ~0ULL);
address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as"); address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
/* Device translation context cache */
s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
riscv_iommu_ctx_equal,
g_free, NULL);
s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
riscv_iommu_iot_equal,
g_free, NULL);
s->iommus.le_next = NULL;
s->iommus.le_prev = NULL;
QLIST_INIT(&s->spaces);
} }
static void riscv_iommu_unrealize(DeviceState *dev) static void riscv_iommu_unrealize(DeviceState *dev)
@ -2283,6 +2289,7 @@ static const TypeInfo riscv_iommu_info = {
.name = TYPE_RISCV_IOMMU, .name = TYPE_RISCV_IOMMU,
.parent = TYPE_DEVICE, .parent = TYPE_DEVICE,
.instance_size = sizeof(RISCVIOMMUState), .instance_size = sizeof(RISCVIOMMUState),
.instance_init = riscv_iommu_instance_init,
.class_init = riscv_iommu_class_init, .class_init = riscv_iommu_class_init,
}; };