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hw: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6529 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
parent
090f1fa323
commit
487414f1cb
74 changed files with 257 additions and 545 deletions
422
hw/ppc405_uc.c
422
hw/ppc405_uc.c
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@ -169,13 +169,11 @@ void ppc4xx_plb_init (CPUState *env)
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ppc4xx_plb_t *plb;
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plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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if (plb != NULL) {
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ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc4xx_plb_reset(plb);
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qemu_register_reset(ppc4xx_plb_reset, plb);
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}
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ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
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ppc4xx_plb_reset(plb);
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qemu_register_reset(ppc4xx_plb_reset, plb);
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}
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/*****************************************************************************/
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@ -248,13 +246,11 @@ void ppc4xx_pob_init (CPUState *env)
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ppc4xx_pob_t *pob;
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pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
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if (pob != NULL) {
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ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
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ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
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ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
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qemu_register_reset(ppc4xx_pob_reset, pob);
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ppc4xx_pob_reset(env);
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}
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ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
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ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
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ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
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qemu_register_reset(ppc4xx_pob_reset, pob);
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ppc4xx_pob_reset(env);
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}
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/*****************************************************************************/
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@ -384,16 +380,14 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
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ppc4xx_opba_t *opba;
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opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
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if (opba != NULL) {
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opba->base = offset;
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opba->base = offset;
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#ifdef DEBUG_OPBA
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printf("%s: offset " PADDRX "\n", __func__, offset);
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printf("%s: offset " PADDRX "\n", __func__, offset);
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#endif
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ppc4xx_mmio_register(env, mmio, offset, 0x002,
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opba_read, opba_write, opba);
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qemu_register_reset(ppc4xx_opba_reset, opba);
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ppc4xx_opba_reset(opba);
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}
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ppc4xx_mmio_register(env, mmio, offset, 0x002,
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opba_read, opba_write, opba);
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qemu_register_reset(ppc4xx_opba_reset, opba);
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ppc4xx_opba_reset(opba);
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}
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/*****************************************************************************/
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@ -585,14 +579,12 @@ void ppc405_ebc_init (CPUState *env)
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ppc4xx_ebc_t *ebc;
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ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
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if (ebc != NULL) {
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ebc_reset(ebc);
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qemu_register_reset(&ebc_reset, ebc);
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ppc_dcr_register(env, EBC0_CFGADDR,
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ebc, &dcr_read_ebc, &dcr_write_ebc);
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ppc_dcr_register(env, EBC0_CFGDATA,
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ebc, &dcr_read_ebc, &dcr_write_ebc);
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}
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ebc_reset(ebc);
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qemu_register_reset(&ebc_reset, ebc);
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ppc_dcr_register(env, EBC0_CFGADDR,
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ebc, &dcr_read_ebc, &dcr_write_ebc);
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ppc_dcr_register(env, EBC0_CFGDATA,
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ebc, &dcr_read_ebc, &dcr_write_ebc);
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}
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/*****************************************************************************/
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@ -678,59 +670,57 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
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ppc405_dma_t *dma;
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dma = qemu_mallocz(sizeof(ppc405_dma_t));
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if (dma != NULL) {
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memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
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ppc405_dma_reset(dma);
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qemu_register_reset(&ppc405_dma_reset, dma);
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ppc_dcr_register(env, DMA0_CR0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CR1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CR2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CR3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SR,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SGC,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SLP,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_POL,
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dma, &dcr_read_dma, &dcr_write_dma);
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}
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memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
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ppc405_dma_reset(dma);
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qemu_register_reset(&ppc405_dma_reset, dma);
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ppc_dcr_register(env, DMA0_CR0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG0,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CR1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG1,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CR2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG2,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CR3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_CT3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_DA3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SA3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SG3,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SR,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SGC,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_SLP,
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dma, &dcr_read_dma, &dcr_write_dma);
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ppc_dcr_register(env, DMA0_POL,
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dma, &dcr_read_dma, &dcr_write_dma);
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}
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/*****************************************************************************/
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@ -845,16 +835,14 @@ void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
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ppc405_gpio_t *gpio;
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gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
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if (gpio != NULL) {
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gpio->base = offset;
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ppc405_gpio_reset(gpio);
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qemu_register_reset(&ppc405_gpio_reset, gpio);
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gpio->base = offset;
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ppc405_gpio_reset(gpio);
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qemu_register_reset(&ppc405_gpio_reset, gpio);
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#ifdef DEBUG_GPIO
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printf("%s: offset " PADDRX "\n", __func__, offset);
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printf("%s: offset " PADDRX "\n", __func__, offset);
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#endif
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ppc4xx_mmio_register(env, mmio, offset, 0x038,
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ppc405_gpio_read, ppc405_gpio_write, gpio);
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}
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ppc4xx_mmio_register(env, mmio, offset, 0x038,
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ppc405_gpio_read, ppc405_gpio_write, gpio);
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}
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/*****************************************************************************/
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@ -1038,19 +1026,17 @@ void ppc405_ocm_init (CPUState *env, unsigned long offset)
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ppc405_ocm_t *ocm;
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ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
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if (ocm != NULL) {
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ocm->offset = offset;
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ocm_reset(ocm);
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qemu_register_reset(&ocm_reset, ocm);
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ppc_dcr_register(env, OCM0_ISARC,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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ppc_dcr_register(env, OCM0_ISACNTL,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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ppc_dcr_register(env, OCM0_DSARC,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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ppc_dcr_register(env, OCM0_DSACNTL,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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}
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ocm->offset = offset;
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ocm_reset(ocm);
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qemu_register_reset(&ocm_reset, ocm);
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ppc_dcr_register(env, OCM0_ISARC,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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ppc_dcr_register(env, OCM0_ISACNTL,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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ppc_dcr_register(env, OCM0_DSARC,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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ppc_dcr_register(env, OCM0_DSACNTL,
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ocm, &dcr_read_ocm, &dcr_write_ocm);
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}
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/*****************************************************************************/
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@ -1286,17 +1272,15 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
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ppc4xx_i2c_t *i2c;
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i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
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if (i2c != NULL) {
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i2c->base = offset;
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i2c->irq = irq;
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ppc4xx_i2c_reset(i2c);
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i2c->base = offset;
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i2c->irq = irq;
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ppc4xx_i2c_reset(i2c);
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#ifdef DEBUG_I2C
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printf("%s: offset " PADDRX "\n", __func__, offset);
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printf("%s: offset " PADDRX "\n", __func__, offset);
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#endif
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ppc4xx_mmio_register(env, mmio, offset, 0x011,
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i2c_read, i2c_write, i2c);
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qemu_register_reset(ppc4xx_i2c_reset, i2c);
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}
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ppc4xx_mmio_register(env, mmio, offset, 0x011,
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i2c_read, i2c_write, i2c);
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qemu_register_reset(ppc4xx_i2c_reset, i2c);
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}
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/*****************************************************************************/
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@ -1568,19 +1552,17 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
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int i;
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gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
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if (gpt != NULL) {
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gpt->base = offset;
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for (i = 0; i < 5; i++)
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gpt->irqs[i] = irqs[i];
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gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
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ppc4xx_gpt_reset(gpt);
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gpt->base = offset;
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for (i = 0; i < 5; i++)
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gpt->irqs[i] = irqs[i];
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gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
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ppc4xx_gpt_reset(gpt);
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#ifdef DEBUG_GPT
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printf("%s: offset " PADDRX "\n", __func__, offset);
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printf("%s: offset " PADDRX "\n", __func__, offset);
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#endif
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ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
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gpt_read, gpt_write, gpt);
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qemu_register_reset(ppc4xx_gpt_reset, gpt);
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}
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ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
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gpt_read, gpt_write, gpt);
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qemu_register_reset(ppc4xx_gpt_reset, gpt);
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}
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/*****************************************************************************/
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@ -1802,50 +1784,48 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
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int i;
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mal = qemu_mallocz(sizeof(ppc40x_mal_t));
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if (mal != NULL) {
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for (i = 0; i < 4; i++)
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mal->irqs[i] = irqs[i];
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ppc40x_mal_reset(mal);
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qemu_register_reset(&ppc40x_mal_reset, mal);
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ppc_dcr_register(env, MAL0_CFG,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_ESR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_IER,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_TXCASR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_TXCARR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_TXEOBISR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_TXDEIR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_RXCASR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_RXCARR,
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mal, &dcr_read_mal, &dcr_write_mal);
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ppc_dcr_register(env, MAL0_RXEOBISR,
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mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXDEIR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP0R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP1R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP2R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP3R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXCTP0R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXCTP1R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RCBS0,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RCBS1,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
}
|
||||
for (i = 0; i < 4; i++)
|
||||
mal->irqs[i] = irqs[i];
|
||||
ppc40x_mal_reset(mal);
|
||||
qemu_register_reset(&ppc40x_mal_reset, mal);
|
||||
ppc_dcr_register(env, MAL0_CFG,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_ESR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_IER,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCASR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCARR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXEOBISR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXDEIR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXCASR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXCARR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXEOBISR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXDEIR,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP0R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP1R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP2R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_TXCTP3R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXCTP0R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RXCTP1R,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RCBS0,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
ppc_dcr_register(env, MAL0_RCBS1,
|
||||
mal, &dcr_read_mal, &dcr_write_mal);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -2170,31 +2150,29 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
|
|||
ppc405cr_cpc_t *cpc;
|
||||
|
||||
cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
||||
if (cpc != NULL) {
|
||||
memcpy(cpc->clk_setup, clk_setup,
|
||||
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
||||
cpc->sysclk = sysclk;
|
||||
cpc->jtagid = 0x42051049;
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc405cr_clk_init(cpc);
|
||||
qemu_register_reset(ppc405cr_cpc_reset, cpc);
|
||||
ppc405cr_cpc_reset(cpc);
|
||||
}
|
||||
memcpy(cpc->clk_setup, clk_setup,
|
||||
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
||||
cpc->sysclk = sysclk;
|
||||
cpc->jtagid = 0x42051049;
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc405cr_clk_init(cpc);
|
||||
qemu_register_reset(ppc405cr_cpc_reset, cpc);
|
||||
ppc405cr_cpc_reset(cpc);
|
||||
}
|
||||
|
||||
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
||||
|
|
@ -2516,38 +2494,36 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
|
|||
ppc405ep_cpc_t *cpc;
|
||||
|
||||
cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
||||
if (cpc != NULL) {
|
||||
memcpy(cpc->clk_setup, clk_setup,
|
||||
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
||||
cpc->jtagid = 0x20267049;
|
||||
cpc->sysclk = sysclk;
|
||||
ppc405ep_cpc_reset(cpc);
|
||||
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
memcpy(cpc->clk_setup, clk_setup,
|
||||
PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
||||
cpc->jtagid = 0x20267049;
|
||||
cpc->sysclk = sysclk;
|
||||
ppc405ep_cpc_reset(cpc);
|
||||
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
#if 0
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
||||
&dcr_read_epcpc, &dcr_write_epcpc);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue