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target/arm: Advance pc for arch single-step exception

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The size of the code covered by a TranslationBlock cannot be 0;
this is checked via assert in tb_gen_code.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson 2021-11-03 00:03:47 -04:00 • committed by Peter Maydell
parent 258a00e5a4
commit 485088f742
1 changed files with 1 additions and 0 deletions
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target/arm/translate-a64.c
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@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
assert(s->base.num_insns == 1); assert(s->base.num_insns == 1);
gen_swstep_exception(s, 0, 0); gen_swstep_exception(s, 0, 0);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
s->base.pc_next = pc + 4;
return; return;
} }