X86 patches queued in the last few weeks. Mostly code cleanup and changes on

code assigning APIC ID.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJU/gVGAAoJECgHk2+YTcWmGmgQAKE/tDoKt2Uw5BjWxmmU0GFm
 r4m43rcR3xfHdQyEx3iNKSlAQvxcYd/eBM5kb6Ir7wjhqtDfoiVC+bui3VhAsQPk
 kaB+6ryyAGDV2xt1UtgfzEodXl9aw0zofFBafJrtArITAsO5UeuTQhxIuLHwzcF6
 XKkpg7oz3bgRH57gZFi1y5PUdJUpmk4awipE/A4G/y5mERe2W30Ku4JSSxV7+shz
 MLOQF4GjfHBKnfA/PVQbtWQjbKVZRPbGrcg+TmEH+2TGzEMVXeXuqvAgbOGhhlcD
 uJyiCeXf1CD92JIU2JWXejd0SSLLJyf74TiBEhxfFil3gpS+d5RWSCkuR1mmtpR4
 B5NPbhhPZmXJBMIQB9kM0fiW4I8+qPPqFatqEJ78OYhVqUHgY746hnJTc22jK/FK
 e1UxLBREMLAty4aVT3iAaPZo6hM/IMctEOgEhwH15NSQDNXFIqrlM/b5OJ9Iq01Y
 Ah838rv4kRiVQcKoa1Mg8rqBvmw4Cm1MKcYp4sOPhY4/bwx71qagbZG4EAfQ6DP6
 uieN/4hMTuGqf4eHgIjrdAr/4sPPiszYjF6fVwJVh+pCbirWOsRQPx4NnSmIRveU
 CUJuuHCsqWjThMEWVNqe5bm1d32EI0o16ihEBuBl+MqivpmV+4p/bJYvyiC1vJw7
 UatzprZMm2Az2RL6W6Mw
 =iDzB
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging

X86 patches queued in the last few weeks. Mostly code cleanup and changes on
code assigning APIC ID.

# gpg: Signature made Mon Mar  9 20:40:38 2015 GMT using RSA key ID 984DC5A6
# gpg: Can't check signature: public key not found

* remotes/ehabkost/tags/x86-pull-request:
  target-i386: Require APIC ID to be explicitly set before CPU realize
  target-i386: Move APIC ID compatibility code to pc.c
  target-i386: Move CPUX86State::cpuid_apic_id to X86CPU::apic_id
  target-i386: Remove unused APIC ID default code
  target-i386: Eliminate unnecessary get_cpuid_vendor() function
  target-i386: Simplify listflags() function
  target-i386: Move topology.h to include/hw/i386

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-03-11 11:12:35 +00:00
commit 4841237141
8 changed files with 76 additions and 92 deletions

View file

@ -25,6 +25,8 @@
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/i386/apic.h"
#include "hw/i386/topology.h"
#include "sysemu/cpus.h"
#include "hw/block/fdc.h"
#include "hw/ide.h"
#include "hw/pci/pci.h"
@ -629,6 +631,39 @@ bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
return false;
}
/* Enables contiguous-apic-ID mode, for compatibility */
static bool compat_apic_id_mode;
void enable_compat_apic_id_mode(void)
{
compat_apic_id_mode = true;
}
/* Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
* alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
* no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
* all CPUs up to max_cpus.
*/
static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
{
uint32_t correct_id;
static bool warned;
correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
if (compat_apic_id_mode) {
if (cpu_index != correct_id && !warned) {
error_report("APIC IDs set in compatibility mode, "
"CPU topology won't match the configuration");
warned = true;
}
return cpu_index;
} else {
return correct_id;
}
}
/* Calculates the limit to CPU APIC ID values
*
* This function returns the limit for the APIC ID value, so that all