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target/riscv: Separate priv from mmu_idx

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Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fei Wu <fei2.wu@intel.com>
Message-Id: <20230324054154.414846-2-fei2.wu@intel.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Fei Wu 2023-04-12 13:43:14 +02:00 • committed by Alistair Francis
parent 4acaa133b1
commit 47debc7280
5 changed files with 8 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

14
target/riscv/insn_trans/trans_xthead.c.inc
View file

@ -263,25 +263,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
/* XTheadCmo */
static inline int priv_level(DisasContext *ctx)
{
#ifdef CONFIG_USER_ONLY
return PRV_U;
#else
/* Priv level is part of mem_idx. */
return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK;
#endif
}
/* Test if priv level is M, S, or U (cannot fail). */
#define REQUIRE_PRIV_MSU(ctx)
/* Test if priv level is M or S. */
#define REQUIRE_PRIV_MS(ctx) \
do { \
int priv = priv_level(ctx); \
if (!(priv == PRV_M || \
priv == PRV_S)) { \
if (ctx->priv == PRV_U) { \
return false; \
} \
} while (0)