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softfloat: Fix the incorrect computation in float32_exp2

Browse source 
tcg: Remove compatability helpers for qemu ld/st
 target/alpha: Remove TARGET_ALIGNED_ONLY
 target/hppa: Remove TARGET_ALIGNED_ONLY
 target/sparc: Remove TARGET_ALIGNED_ONLY
 tcg: Cleanups preparing to unify calls to qemu_ld/st helpers
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Merge tag 'pull-tcg-20230505' of https://gitlab.com/rth7680/qemu into staging

softfloat: Fix the incorrect computation in float32_exp2
tcg: Remove compatability helpers for qemu ld/st
target/alpha: Remove TARGET_ALIGNED_ONLY
target/hppa: Remove TARGET_ALIGNED_ONLY
target/sparc: Remove TARGET_ALIGNED_ONLY
tcg: Cleanups preparing to unify calls to qemu_ld/st helpers

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# gpg: Signature made Fri 05 May 2023 10:23:33 PM BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230505' of https://gitlab.com/rth7680/qemu: (42 commits)
  tcg: Widen helper_*_st[bw]_mmu val arguments
  tcg: Introduce arg_slot_stk_ofs
  tcg: Replace REG_P with arg_loc_reg_p
  tcg: Move TCGLabelQemuLdst to tcg.c
  tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}
  tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
  tcg/s390x: Introduce HostAddress
  tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}
  tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
  tcg/riscv: Require TCG_TARGET_REG_BITS == 64
  tcg/ppc: Introduce HostAddress
  tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}
  tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}
  tcg/loongarch64: Introduce HostAddress
  tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st}
  tcg/arm: Introduce HostAddress
  tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
  tcg/aarch64: Introduce HostAddress
  tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st}
  tcg/i386: Introduce tcg_out_testi
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-05 22:29:28 +01:00
commit 47d3878422
42 changed files with 1120 additions and 1291 deletions
Download patch file Download diff file Expand all files Collapse all files

38
target/alpha/translate.c
View file

@ -72,7 +72,7 @@ struct DisasContext {
#ifdef CONFIG_USER_ONLY
#define UNALIGN(C) (C)->unalign
#else
#define UNALIGN(C) 0
#define UNALIGN(C) MO_ALIGN
#endif
/* Target-specific return values from translate_one, indicating the
@ -2399,21 +2399,21 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ);
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, addr);
tcg_gen_mov_i64(cpu_lock_value, va);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ);
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, addr);
tcg_gen_mov_i64(cpu_lock_value, va);
break;
@ -2438,11 +2438,13 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */
tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL);
tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
MO_LESL | MO_ALIGN);
break;
case 0xB:
/* Quadword virtual access with protection check (hw_ldq/w) */
tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEUQ);
tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
MO_LEUQ | MO_ALIGN);
break;
case 0xC:
/* Longword virtual access with alt access mode (hw_ldl/a)*/
@ -2453,12 +2455,14 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0xE:
/* Longword virtual access with alternate access mode and
protection checks (hw_ldl/wa) */
tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL);
tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
MO_LESL | MO_ALIGN);
break;
case 0xF:
/* Quadword virtual access with alternate access mode and
protection checks (hw_ldq/wa) */
tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEUQ);
tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
MO_LEUQ | MO_ALIGN);
break;
}
break;
@ -2659,7 +2663,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
vb = load_gpr(ctx, rb);
tmp = tcg_temp_new();
tcg_gen_addi_i64(tmp, vb, disp12);
tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL);
tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x1:
/* Quadword physical access */
@ -2667,17 +2671,17 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
vb = load_gpr(ctx, rb);
tmp = tcg_temp_new();
tcg_gen_addi_i64(tmp, vb, disp12);
tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ);
tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x2:
/* Longword physical access with lock */
ret = gen_store_conditional(ctx, ra, rb, disp12,
MMU_PHYS_IDX, MO_LESL);
MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x3:
/* Quadword physical access with lock */
ret = gen_store_conditional(ctx, ra, rb, disp12,
MMU_PHYS_IDX, MO_LEUQ);
MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x4:
/* Longword virtual access */
@ -2771,11 +2775,11 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x2A:
/* LDL_L */
gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
gen_load_int(ctx, ra, rb, disp16, MO_LESL | MO_ALIGN, 0, 1);
break;
case 0x2B:
/* LDQ_L */
gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 0, 1);
gen_load_int(ctx, ra, rb, disp16, MO_LEUQ | MO_ALIGN, 0, 1);
break;
case 0x2C:
/* STL */
@ -2788,12 +2792,12 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x2E:
/* STL_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
ctx->mem_idx, MO_LESL);
ctx->mem_idx, MO_LESL | MO_ALIGN);
break;
case 0x2F:
/* STQ_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
ctx->mem_idx, MO_LEUQ);
ctx->mem_idx, MO_LEUQ | MO_ALIGN);
break;
case 0x30:
/* BR */

16
target/avr/translate.c
View file

@ -1492,7 +1492,7 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr)
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullwr(cpu_env, data, addr);
} else {
tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */
tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
}
@ -1501,7 +1501,7 @@ static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr)
if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) {
gen_helper_fullrd(data, cpu_env, addr);
} else {
tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */
tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB);
}
}
@ -1979,7 +1979,7 @@ static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a)
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
tcg_gen_or_tl(addr, addr, L);
tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@ -1996,7 +1996,7 @@ static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a)
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
tcg_gen_or_tl(addr, addr, L);
tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@ -2013,7 +2013,7 @@ static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a)
tcg_gen_shli_tl(addr, H, 8); /* addr = H:L */
tcg_gen_or_tl(addr, addr, L);
tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
tcg_gen_andi_tl(L, addr, 0xff);
tcg_gen_shri_tl(addr, addr, 8);
@ -2045,7 +2045,7 @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a)
TCGv Rd = cpu_r[0];
TCGv addr = gen_get_zaddr();
tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@ -2058,7 +2058,7 @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a)
TCGv Rd = cpu_r[a->rd];
TCGv addr = gen_get_zaddr();
tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
return true;
}
@ -2071,7 +2071,7 @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a)
TCGv Rd = cpu_r[a->rd];
TCGv addr = gen_get_zaddr();
tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */
tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB);
tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */
gen_set_zaddr(addr);
return true;

18
target/cris/translate_v10.c.inc
View file

@ -80,13 +80,9 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
/* Store only if F flag isn't set */
tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
if (size == 1) {
tcg_gen_qemu_st8(tval, taddr, mem_index);
} else if (size == 2) {
tcg_gen_qemu_st16(tval, taddr, mem_index);
} else {
tcg_gen_qemu_st32(tval, taddr, mem_index);
}
tcg_gen_qemu_st_tl(tval, taddr, mem_index, ctz32(size) | MO_TE);
gen_set_label(l1);
tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
@ -109,13 +105,7 @@ static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
return;
}
if (size == 1) {
tcg_gen_qemu_st8(val, addr, mem_index);
} else if (size == 2) {
tcg_gen_qemu_st16(val, addr, mem_index);
} else {
tcg_gen_qemu_st32(val, addr, mem_index);
}
tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE);
}

8
target/hexagon/genptr.c
View file

@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
{
tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}
static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
{
tcg_gen_qemu_ld64(dest, vaddr, mem_index);
tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}
@ -678,7 +678,7 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
{
Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
CHECK_NOSHUF(EA, 8);
tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx);
tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ);
}
static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
@ -1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1));
}
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx);
tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
tcg_gen_addi_tl(src, src, 8);
tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
}

28
target/hexagon/idef-parser/parser-helpers.c
View file

@ -1737,36 +1737,34 @@ void gen_load_cancel(Context *c, YYLTYPE *locp)
void gen_load(Context *c, YYLTYPE *locp, HexValue *width,
HexSignedness signedness, HexValue *ea, HexValue *dst)
{
char size_suffix[4] = {0};
const char *sign_suffix;
unsigned dst_bit_width;
unsigned src_bit_width;
/* Memop width is specified in the load macro */
assert_signedness(c, locp, signedness);
sign_suffix = (width->imm.value > 4)
? ""
: ((signedness == UNSIGNED) ? "u" : "s");
/* If dst is a variable, assert that is declared and load the type info */
if (dst->type == VARID) {
find_variable(c, locp, dst, dst);
}
snprintf(size_suffix, 4, "%" PRIu64, width->imm.value * 8);
src_bit_width = width->imm.value * 8;
dst_bit_width = MAX(dst->bit_width, 32);
/* Lookup the effective address EA */
find_variable(c, locp, ea, ea);
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\n");
OUT(c, locp, "process_store(ctx, 1);\n");
OUT(c, locp, "}\n");
OUT(c, locp, "tcg_gen_qemu_ld", size_suffix, sign_suffix);
OUT(c, locp, "tcg_gen_qemu_ld_i", &dst_bit_width);
OUT(c, locp, "(");
if (dst->bit_width > width->imm.value * 8) {
/*
* Cast to the correct TCG type if necessary, to avoid implict cast
* warnings. This is needed when the width of the destination var is
* larger than the size of the requested load.
*/
OUT(c, locp, "(TCGv) ");
OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx, MO_", &src_bit_width);
if (signedness == SIGNED) {
OUT(c, locp, " | MO_SIGN");
}
OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx);\n");
OUT(c, locp, " | MO_TE);\n");
}
void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,

14
target/hexagon/macros.h
View file

@ -99,37 +99,37 @@
#define MEM_LOAD1s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 1); \
tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \
} while (0)
#define MEM_LOAD1u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 1); \
tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \
} while (0)
#define MEM_LOAD2s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 2); \
tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \
} while (0)
#define MEM_LOAD2u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 2); \
tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \
} while (0)
#define MEM_LOAD4s(DST, VA) \
do { \
CHECK_NOSHUF(VA, 4); \
tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \
} while (0)
#define MEM_LOAD4u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 4); \
tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \
} while (0)
#define MEM_LOAD8u(DST, VA) \
do { \
CHECK_NOSHUF(VA, 8); \
tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \
} while (0)
#define MEM_STORE1_FUNC(X) \

32
target/hexagon/translate.c
View file

@ -627,27 +627,27 @@ void process_store(DisasContext *ctx, int slot_num)
switch (ctx->store_width[slot_num]) {
case 1:
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st8(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_UB);
break;
case 2:
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st16(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUW);
break;
case 4:
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st32(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
tcg_gen_qemu_st_tl(hex_store_val32[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUL);
break;
case 8:
gen_check_store_width(ctx, slot_num);
tcg_gen_qemu_st64(hex_store_val64[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx);
tcg_gen_qemu_st_i64(hex_store_val64[slot_num],
hex_store_addr[slot_num],
ctx->mem_idx, MO_TEUQ);
break;
default:
{
@ -693,13 +693,13 @@ static void process_dczeroa(DisasContext *ctx)
TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
}
}

2
target/hppa/translate.c
View file

@ -271,7 +271,7 @@ typedef struct DisasContext {
#ifdef CONFIG_USER_ONLY
#define UNALIGN(C) (C)->unalign
#else
#define UNALIGN(C) 0
#define UNALIGN(C) MO_ALIGN
#endif
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */

76
target/m68k/translate.c
View file

@ -304,23 +304,14 @@ static inline void gen_addr_fault(DisasContext *s)
static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
int sign, int index)
{
TCGv tmp;
tmp = tcg_temp_new_i32();
switch(opsize) {
TCGv tmp = tcg_temp_new_i32();
switch (opsize) {
case OS_BYTE:
if (sign)
tcg_gen_qemu_ld8s(tmp, addr, index);
else
tcg_gen_qemu_ld8u(tmp, addr, index);
break;
case OS_WORD:
if (sign)
tcg_gen_qemu_ld16s(tmp, addr, index);
else
tcg_gen_qemu_ld16u(tmp, addr, index);
break;
case OS_LONG:
tcg_gen_qemu_ld32u(tmp, addr, index);
tcg_gen_qemu_ld_tl(tmp, addr, index,
opsize | (sign ? MO_SIGN : 0) | MO_TE);
break;
default:
g_assert_not_reached();
@ -332,15 +323,11 @@ static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
int index)
{
switch(opsize) {
switch (opsize) {
case OS_BYTE:
tcg_gen_qemu_st8(val, addr, index);
break;
case OS_WORD:
tcg_gen_qemu_st16(val, addr, index);
break;
case OS_LONG:
tcg_gen_qemu_st32(val, addr, index);
tcg_gen_qemu_st_tl(val, addr, index, opsize | MO_TE);
break;
default:
g_assert_not_reached();
@ -971,23 +958,16 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
tcg_gen_qemu_ld8s(tmp, addr, index);
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_WORD:
tcg_gen_qemu_ld16s(tmp, addr, index);
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_LONG:
tcg_gen_qemu_ld32u(tmp, addr, index);
tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_SINGLE:
tcg_gen_qemu_ld32u(tmp, addr, index);
tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_helper_extf32(cpu_env, fp, tmp);
break;
case OS_DOUBLE:
tcg_gen_qemu_ld64(t64, addr, index);
tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
gen_helper_extf64(cpu_env, fp, t64);
break;
case OS_EXTENDED:
@ -995,11 +975,11 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
tcg_gen_qemu_ld32u(tmp, addr, index);
tcg_gen_qemu_ld_i32(tmp, addr, index, MO_TEUL);
tcg_gen_shri_i32(tmp, tmp, 16);
tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
tcg_gen_addi_i32(tmp, addr, 4);
tcg_gen_qemu_ld64(t64, tmp, index);
tcg_gen_qemu_ld_i64(t64, tmp, index, MO_TEUQ);
tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
break;
case OS_PACKED:
@ -1024,24 +1004,18 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
gen_helper_reds32(tmp, cpu_env, fp);
tcg_gen_qemu_st8(tmp, addr, index);
break;
case OS_WORD:
gen_helper_reds32(tmp, cpu_env, fp);
tcg_gen_qemu_st16(tmp, addr, index);
break;
case OS_LONG:
gen_helper_reds32(tmp, cpu_env, fp);
tcg_gen_qemu_st32(tmp, addr, index);
tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
break;
case OS_SINGLE:
gen_helper_redf32(tmp, cpu_env, fp);
tcg_gen_qemu_st32(tmp, addr, index);
tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
break;
case OS_DOUBLE:
gen_helper_redf64(t64, cpu_env, fp);
tcg_gen_qemu_st64(t64, addr, index);
tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
@ -1050,10 +1024,10 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
}
tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
tcg_gen_shli_i32(tmp, tmp, 16);
tcg_gen_qemu_st32(tmp, addr, index);
tcg_gen_qemu_st_i32(tmp, addr, index, MO_TEUL);
tcg_gen_addi_i32(tmp, addr, 4);
tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
tcg_gen_qemu_st64(t64, tmp, index);
tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ);
break;
case OS_PACKED:
/*
@ -2079,14 +2053,14 @@ DISAS_INSN(movep)
if (insn & 0x80) {
for ( ; i > 0 ; i--) {
tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
tcg_gen_qemu_st_i32(dbuf, abuf, IS_USER(s), MO_UB);
if (i > 1) {
tcg_gen_addi_i32(abuf, abuf, 2);
}
}
} else {
for ( ; i > 0 ; i--) {
tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
tcg_gen_qemu_ld_tl(dbuf, abuf, IS_USER(s), MO_UB);
tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
if (i > 1) {
tcg_gen_addi_i32(abuf, abuf, 2);
@ -4337,14 +4311,14 @@ static void m68k_copy_line(TCGv dst, TCGv src, int index)
t1 = tcg_temp_new_i64();
tcg_gen_andi_i32(addr, src, ~15);
tcg_gen_qemu_ld64(t0, addr, index);
tcg_gen_qemu_ld_i64(t0, addr, index, MO_TEUQ);
tcg_gen_addi_i32(addr, addr, 8);
tcg_gen_qemu_ld64(t1, addr, index);
tcg_gen_qemu_ld_i64(t1, addr, index, MO_TEUQ);
tcg_gen_andi_i32(addr, dst, ~15);
tcg_gen_qemu_st64(t0, addr, index);
tcg_gen_qemu_st_i64(t0, addr, index, MO_TEUQ);
tcg_gen_addi_i32(addr, addr, 8);
tcg_gen_qemu_st64(t1, addr, index);
tcg_gen_qemu_st_i64(t1, addr, index, MO_TEUQ);
}
DISAS_INSN(move16_reg)
@ -4767,7 +4741,7 @@ static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
tmp = tcg_temp_new();
gen_load_fcr(s, tmp, reg);
tcg_gen_qemu_st32(tmp, addr, index);
tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
}
static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
@ -4776,7 +4750,7 @@ static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
TCGv tmp;
tmp = tcg_temp_new();
tcg_gen_qemu_ld32u(tmp, addr, index);
tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_store_fcr(s, tmp, reg);
}

2
target/mips/tcg/nanomips_translate.c.inc
View file

@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset);
tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx);
tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ);
if (cpu_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {

8
target/mips/tcg/translate.c
View file

@ -1949,13 +1949,13 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
/* load/store instructions. */
#ifdef CONFIG_USER_ONLY
#define OP_LD_ATOMIC(insn, fname) \
#define OP_LD_ATOMIC(insn, memop) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
TCGv t0 = tcg_temp_new(); \
tcg_gen_mov_tl(t0, arg1); \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); \
tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); \
}
@ -1967,9 +1967,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
OP_LD_ATOMIC(ll, ld32s);
OP_LD_ATOMIC(ll, MO_TESL);
#if defined(TARGET_MIPS64)
OP_LD_ATOMIC(lld, ld64);
OP_LD_ATOMIC(lld, MO_TEUQ);
#endif
#undef OP_LD_ATOMIC

152
target/s390x/tcg/translate.c
View file

@ -1973,32 +1973,24 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
{
int l = get_field(s, l1);
TCGv_i32 vl;
MemOp mop;
switch (l + 1) {
case 1:
tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
break;
case 2:
tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
break;
case 4:
tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
break;
case 8:
tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
break;
mop = ctz32(l + 1) | MO_TE;
tcg_gen_qemu_ld_tl(cc_src, o->addr1, get_mem_index(s), mop);
tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);
gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
return DISAS_NEXT;
default:
vl = tcg_constant_i32(l);
gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
}
gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
return DISAS_NEXT;
}
static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
@ -2199,7 +2191,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
TCGv_i32 t2 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t2, o->in1);
gen_helper_cvd(t1, t2);
tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
return DISAS_NEXT;
}
@ -2457,7 +2449,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
switch (m3) {
case 0xf:
/* Effectively a 32-bit load. */
tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
len = 32;
goto one_insert;
@ -2465,7 +2457,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
case 0x6:
case 0x3:
/* Effectively a 16-bit load. */
tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
len = 16;
goto one_insert;
@ -2474,7 +2466,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
case 0x2:
case 0x1:
/* Effectively an 8-bit load. */
tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
len = 8;
goto one_insert;
@ -2490,7 +2482,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
ccm = 0;
while (m3) {
if (m3 & 0x8) {
tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
ccm |= 0xffull << pos;
@ -2746,25 +2738,25 @@ static DisasJumpType op_llgt(DisasContext *s, DisasOps *o)
static DisasJumpType op_ld8s(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB);
return DISAS_NEXT;
}
static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB);
return DISAS_NEXT;
}
static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW);
return DISAS_NEXT;
}
static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW);
return DISAS_NEXT;
}
@ -2803,7 +2795,7 @@ static DisasJumpType op_lat(DisasContext *s, DisasOps *o)
static DisasJumpType op_lgat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ);
/* The value is stored even in case of trap. */
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
@ -2825,7 +2817,8 @@ static DisasJumpType op_lfhat(DisasContext *s, DisasOps *o)
static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
/* The value is stored even in case of trap. */
tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
gen_trap(s);
@ -2942,7 +2935,7 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
MO_TEUQ | MO_ALIGN_8);
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ);
gen_helper_load_psw(cpu_env, t1, t2);
return DISAS_NORETURN;
}
@ -2966,7 +2959,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
/* Only one register to read. */
t1 = tcg_temp_new_i64();
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32_i64(r1, t1);
return DISAS_NEXT;
}
@ -2974,9 +2967,9 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
/* First load the values of the first and last registers to trigger
possible page faults. */
t2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
store_reg32_i64(r1, t1);
store_reg32_i64(r3, t2);
@ -2991,7 +2984,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
while (r1 != r3) {
r1 = (r1 + 1) & 15;
tcg_gen_add_i64(o->in2, o->in2, t2);
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32_i64(r1, t1);
}
return DISAS_NEXT;
@ -3006,7 +2999,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
/* Only one register to read. */
t1 = tcg_temp_new_i64();
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32h_i64(r1, t1);
return DISAS_NEXT;
}
@ -3014,9 +3007,9 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
/* First load the values of the first and last registers to trigger
possible page faults. */
t2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
store_reg32h_i64(r1, t1);
store_reg32h_i64(r3, t2);
@ -3031,7 +3024,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
while (r1 != r3) {
r1 = (r1 + 1) & 15;
tcg_gen_add_i64(o->in2, o->in2, t2);
tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
store_reg32h_i64(r1, t1);
}
return DISAS_NEXT;
@ -3045,7 +3038,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
/* Only one register to read. */
if (unlikely(r1 == r3)) {
tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
return DISAS_NEXT;
}
@ -3053,9 +3046,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
possible page faults. */
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15));
tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s));
tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ);
tcg_gen_mov_i64(regs[r1], t1);
/* Only two registers to read. */
@ -3069,7 +3062,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
while (r1 != r3) {
r1 = (r1 + 1) & 15;
tcg_gen_add_i64(o->in2, o->in2, t1);
tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
}
return DISAS_NEXT;
}
@ -3923,15 +3916,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
switch (s->insn->data) {
case 1: /* STOCG */
tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ);
break;
case 0: /* STOC */
tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL);
break;
case 2: /* STOCFH */
h = tcg_temp_new_i64();
tcg_gen_shri_i64(h, regs[r1], 32);
tcg_gen_qemu_st32(h, a, get_mem_index(s));
tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL);
break;
default:
g_assert_not_reached();
@ -4050,7 +4043,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0);
/* load the third operand into r3 before modifying anything */
tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ);
/* subtract CPU timer from first operand and store in GR0 */
gen_helper_stpt(tmp, cpu_env);
@ -4128,9 +4121,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
tcg_gen_shri_i64(c1, c1, 8);
tcg_gen_ori_i64(c2, c2, 0x10000);
tcg_gen_or_i64(c2, c2, todpr);
tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ);
tcg_gen_addi_i64(o->in2, o->in2, 8);
tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ);
/* ??? We don't implement clock states. */
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
@ -4343,7 +4336,7 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
restart, we'll have the wrong SYSTEM MASK in place. */
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, psw_mask, 56);
tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB);
if (s->fields.op == 0xac) {
tcg_gen_andi_i64(psw_mask, psw_mask,
@ -4380,13 +4373,13 @@ static DisasJumpType op_stfle(DisasContext *s, DisasOps *o)
static DisasJumpType op_st8(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB);
return DISAS_NEXT;
}
static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW);
return DISAS_NEXT;
}
@ -4424,7 +4417,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
case 0xf:
/* Effectively a 32-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
break;
case 0xc:
@ -4432,7 +4425,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
case 0x3:
/* Effectively a 16-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
break;
case 0x8:
@ -4441,7 +4434,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
case 0x1:
/* Effectively an 8-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
break;
default:
@ -4450,7 +4443,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
while (m3) {
if (m3 & 0x8) {
tcg_gen_shri_i64(tmp, o->in1, pos);
tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
tcg_gen_addi_i64(o->in2, o->in2, 1);
}
m3 = (m3 << 1) & 0xf;
@ -4469,11 +4462,8 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
TCGv_i64 tsize = tcg_constant_i64(size);
while (1) {
if (size == 8) {
tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
} else {
tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
}
tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s),
size == 8 ? MO_TEUQ : MO_TEUL);
if (r1 == r3) {
break;
}
@ -4494,7 +4484,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
while (1) {
tcg_gen_shl_i64(t, regs[r1], t32);
tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL);
if (r1 == r3) {
break;
}
@ -4804,28 +4794,28 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
l++;
while (l >= 8) {
tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UQ);
l -= 8;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 8);
}
}
if (l >= 4) {
tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UL);
l -= 4;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 4);
}
}
if (l >= 2) {
tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UW);
l -= 2;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 2);
}
}
if (l) {
tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB);
}
gen_op_movi_cc(s, 0);
return DISAS_NEXT;
@ -5314,13 +5304,13 @@ static void wout_cond_e1e2(DisasContext *s, DisasOps *o)
static void wout_m1_8(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB);
}
#define SPEC_wout_m1_8 0
static void wout_m1_16(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW);
}
#define SPEC_wout_m1_16 0
@ -5334,7 +5324,7 @@ static void wout_m1_16a(DisasContext *s, DisasOps *o)
static void wout_m1_32(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL);
}
#define SPEC_wout_m1_32 0
@ -5348,7 +5338,7 @@ static void wout_m1_32a(DisasContext *s, DisasOps *o)
static void wout_m1_64(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ);
}
#define SPEC_wout_m1_64 0
@ -5362,7 +5352,7 @@ static void wout_m1_64a(DisasContext *s, DisasOps *o)
static void wout_m2_32(DisasContext *s, DisasOps *o)
{
tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
}
#define SPEC_wout_m2_32 0
@ -5557,7 +5547,7 @@ static void in1_m1_8u(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB);
}
#define SPEC_in1_m1_8u 0
@ -5565,7 +5555,7 @@ static void in1_m1_16s(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW);
}
#define SPEC_in1_m1_16s 0
@ -5573,7 +5563,7 @@ static void in1_m1_16u(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW);
}
#define SPEC_in1_m1_16u 0
@ -5581,7 +5571,7 @@ static void in1_m1_32s(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL);
}
#define SPEC_in1_m1_32s 0
@ -5589,7 +5579,7 @@ static void in1_m1_32u(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL);
}
#define SPEC_in1_m1_32u 0
@ -5597,7 +5587,7 @@ static void in1_m1_64(DisasContext *s, DisasOps *o)
{
in1_la1(s, o);
o->in1 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ);
}
#define SPEC_in1_m1_64 0
@ -5811,35 +5801,35 @@ static void in2_sh(DisasContext *s, DisasOps *o)
static void in2_m2_8u(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB);
}
#define SPEC_in2_m2_8u 0
static void in2_m2_16s(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW);
}
#define SPEC_in2_m2_16s 0
static void in2_m2_16u(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW);
}
#define SPEC_in2_m2_16u 0
static void in2_m2_32s(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL);
}
#define SPEC_in2_m2_32s 0
static void in2_m2_32u(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL);
}
#define SPEC_in2_m2_32u 0
@ -5855,14 +5845,14 @@ static void in2_m2_32ua(DisasContext *s, DisasOps *o)
static void in2_m2_64(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
}
#define SPEC_in2_m2_64 0
static void in2_m2_64w(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
}
#define SPEC_in2_m2_64w 0
@ -5879,14 +5869,14 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o)
static void in2_mri2_16s(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
tcg_gen_qemu_ld16s(o->in2, gen_ri2(s), get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW);
}
#define SPEC_in2_mri2_16s 0
static void in2_mri2_16u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
tcg_gen_qemu_ld16u(o->in2, gen_ri2(s), get_mem_index(s));
tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW);
}
#define SPEC_in2_mri2_16u 0

10
target/sparc/ldst_helper.c
View file

@ -593,6 +593,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_addr = addr;
#endif
MemOpIdx oi;
do_check_align(env, addr, size - 1, GETPC());
switch (asi) {
@ -692,19 +693,20 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
break;
case ASI_KERNELTXT: /* Supervisor code access */
oi = make_memop_idx(memop, cpu_mmu_index(env, true));
switch (size) {
case 1:
ret = cpu_ldub_code(env, addr);
ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());
break;
case 2:
ret = cpu_lduw_code(env, addr);
ret = cpu_ldw_code_mmu(env, addr, oi, GETPC());
break;
default:
case 4:
ret = cpu_ldl_code(env, addr);
ret = cpu_ldl_code_mmu(env, addr, oi, GETPC());
break;
case 8:
ret = cpu_ldq_code(env, addr);
ret = cpu_ldq_code_mmu(env, addr, oi, GETPC());
break;
}
break;

85
target/sparc/translate.c
View file

@ -1899,7 +1899,7 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
TCGv addr, int mmu_idx, MemOp memop)
{
gen_address_mask(dc, addr);
tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN);
}
static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
@ -2155,12 +2155,12 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
break;
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN);
break;
default:
{
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
TCGv_i32 r_mop = tcg_constant_i32(memop);
TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
save_state(dc);
#ifdef TARGET_SPARC64
@ -2201,7 +2201,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
/* fall through */
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN);
break;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
case GET_ASI_BCOPY:
@ -2233,7 +2233,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
default:
{
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
TCGv_i32 r_mop = tcg_constant_i32(memop & MO_SIZE);
TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
save_state(dc);
#ifdef TARGET_SPARC64
@ -2283,7 +2283,7 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
case GET_ASI_DIRECT:
oldv = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
da.mem_idx, da.memop);
da.mem_idx, da.memop | MO_ALIGN);
gen_store_gpr(dc, rd, oldv);
break;
default:
@ -2347,7 +2347,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
switch (size) {
case 4:
d32 = gen_dest_fpr_F(dc);
tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
gen_store_fpr_F(dc, rd, d32);
break;
case 8:
@ -2397,7 +2397,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
/* Valid for lddfa only. */
if (size == 8) {
gen_address_mask(dc, addr);
tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
da.memop | MO_ALIGN);
} else {
gen_exception(dc, TT_ILL_INSN);
}
@ -2406,7 +2407,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
default:
{
TCGv_i32 r_asi = tcg_constant_i32(da.asi);
TCGv_i32 r_mop = tcg_constant_i32(da.memop);
TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN);
save_state(dc);
/* According to the table in the UA2011 manual, the only
@ -2454,7 +2455,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
switch (size) {
case 4:
d32 = gen_load_fpr_F(dc, rd);
tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
break;
case 8:
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
@ -2506,7 +2507,8 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
/* Valid for stdfa only. */
if (size == 8) {
gen_address_mask(dc, addr);
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
da.memop | MO_ALIGN);
} else {
gen_exception(dc, TT_ILL_INSN);
}
@ -2543,7 +2545,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
TCGv_i64 tmp = tcg_temp_new_i64();
gen_address_mask(dc, addr);
tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN);
/* Note that LE ldda acts as if each 32-bit register
result is byte swapped. Having just performed one
@ -2613,7 +2615,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
tcg_gen_concat32_i64(t64, hi, lo);
}
gen_address_mask(dc, addr);
tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
}
break;
@ -2651,7 +2653,7 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
case GET_ASI_DIRECT:
oldv = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
da.mem_idx, da.memop);
da.mem_idx, da.memop | MO_ALIGN);
gen_store_gpr(dc, rd, oldv);
break;
default:
@ -2678,7 +2680,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
return;
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
break;
default:
{
@ -2710,7 +2712,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
break;
case GET_ASI_DIRECT:
gen_address_mask(dc, addr);
tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN);
break;
case GET_ASI_BFILL:
/* Store 32 bytes of T64 to ADDR. */
@ -5179,15 +5181,18 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
switch (xop) {
case 0x0: /* ld, V9 lduw, load unsigned word */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TEUL | MO_ALIGN);
break;
case 0x1: /* ldub, load unsigned byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_UB);
break;
case 0x2: /* lduh, load unsigned halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TEUW | MO_ALIGN);
break;
case 0x3: /* ldd, load double word */
if (rd & 1)
@ -5197,7 +5202,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_address_mask(dc, cpu_addr);
t64 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_i64(t64, cpu_addr,
dc->mem_idx, MO_TEUQ | MO_ALIGN);
tcg_gen_trunc_i64_tl(cpu_val, t64);
tcg_gen_ext32u_tl(cpu_val, cpu_val);
gen_store_gpr(dc, rd + 1, cpu_val);
@ -5208,11 +5214,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x9: /* ldsb, load signed byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB);
break;
case 0xa: /* ldsh, load signed halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TESW | MO_ALIGN);
break;
case 0xd: /* ldstub */
gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
@ -5266,11 +5273,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#ifdef TARGET_SPARC64
case 0x08: /* V9 ldsw */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TESL | MO_ALIGN);
break;
case 0x0b: /* V9 ldx */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_ld_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TEUQ | MO_ALIGN);
break;
case 0x18: /* V9 ldswa */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
@ -5321,7 +5330,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_address_mask(dc, cpu_addr);
cpu_dst_32 = gen_dest_fpr_F(dc);
tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
dc->mem_idx, MO_TEUL);
dc->mem_idx, MO_TEUL | MO_ALIGN);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x21: /* ldfsr, V9 ldxfsr */
@ -5330,14 +5339,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (rd == 1) {
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(t64, cpu_addr,
dc->mem_idx, MO_TEUQ);
dc->mem_idx, MO_TEUQ | MO_ALIGN);
gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
break;
}
#endif
cpu_dst_32 = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
dc->mem_idx, MO_TEUL);
dc->mem_idx, MO_TEUL | MO_ALIGN);
gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
break;
case 0x22: /* ldqf, load quad fpreg */
@ -5369,15 +5378,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
switch (xop) {
case 0x4: /* st, store word */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TEUL | MO_ALIGN);
break;
case 0x5: /* stb, store byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB);
break;
case 0x6: /* sth, store halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TEUW | MO_ALIGN);
break;
case 0x7: /* std, store double word */
if (rd & 1)
@ -5390,7 +5401,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
lo = gen_load_gpr(dc, rd + 1);
t64 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t64, lo, cpu_val);
tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_i64(t64, cpu_addr,
dc->mem_idx, MO_TEUQ | MO_ALIGN);
}
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
@ -5413,7 +5425,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
#ifdef TARGET_SPARC64
case 0x0e: /* V9 stx */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_tl(cpu_val, cpu_addr,
dc->mem_idx, MO_TEUQ | MO_ALIGN);
break;
case 0x1e: /* V9 stxa */
gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
@ -5431,18 +5444,20 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_address_mask(dc, cpu_addr);
cpu_src1_32 = gen_load_fpr_F(dc, rd);
tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
dc->mem_idx, MO_TEUL);
dc->mem_idx, MO_TEUL | MO_ALIGN);
break;
case 0x25: /* stfsr, V9 stxfsr */
{
#ifdef TARGET_SPARC64
gen_address_mask(dc, cpu_addr);
if (rd == 1) {
tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
dc->mem_idx, MO_TEUQ | MO_ALIGN);
break;
}
#endif
tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr,
dc->mem_idx, MO_TEUL | MO_ALIGN);
}
break;
case 0x26:

4
target/xtensa/translate.c
View file

@ -1549,7 +1549,7 @@ static void translate_dcache(DisasContext *dc, const OpcodeArg arg[],
TCGv_i32 res = tcg_temp_new_i32();
tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm);
tcg_gen_qemu_ld8u(res, addr, dc->cring);
tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB);
}
static void translate_depbits(DisasContext *dc, const OpcodeArg arg[],
@ -1726,7 +1726,7 @@ static void translate_l32r(DisasContext *dc, const OpcodeArg arg[],
} else {
tmp = tcg_constant_i32(arg[1].imm);
}
tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring);
tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL);
}
static void translate_loop(DisasContext *dc, const OpcodeArg arg[],