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target/riscv: Relax debug check for pm write

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Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:36 +08:00 • committed by Alistair Francis
parent 1191be09a9
commit 47bdec821b
1 changed files with 3 additions and 0 deletions
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3
target/riscv/csr.c
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@ -1556,6 +1556,9 @@ static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
int csr_priv = get_field(csrno, 0x300); int csr_priv = get_field(csrno, 0x300);
int pm_current; int pm_current;
if (env->debugger) {
return false;
}
/* /*
* If priv lvls differ that means we're accessing csr from higher priv lvl, * If priv lvls differ that means we're accessing csr from higher priv lvl,
* so allow the access * so allow the access