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accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state

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Combine 3 different pointer returns into one structure return.

Include a cflags field in TCGTBCPUState, not filled in by
cpu_get_tb_cpu_state, but used by all callers.  This fills
a hole in the structure and is useful in some subroutines.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-04-27 15:32:11 -07:00
parent 5b1c93be57
commit 4759aae432
23 changed files with 218 additions and 176 deletions
Download patch file Download diff file Expand all files Collapse all files

56
accel/tcg/cpu-exec.c
View file

@ -385,9 +385,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
{ {
CPUState *cpu = env_cpu(env); CPUState *cpu = env_cpu(env);
TranslationBlock *tb; TranslationBlock *tb;
vaddr pc;
uint64_t cs_base;
uint32_t flags, cflags;
/* /*
* By definition we've just finished a TB, so I/O is OK. * By definition we've just finished a TB, so I/O is OK.
@ -397,20 +394,21 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
* The next TB, if we chain to it, will clear the flag again. * The next TB, if we chain to it, will clear the flag again.
*/ */
cpu->neg.can_do_io = true; cpu->neg.can_do_io = true;
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
cflags = curr_cflags(cpu); TCGTBCPUState s = cpu_get_tb_cpu_state(cpu);
if (check_for_breakpoints(cpu, pc, &cflags)) { s.cflags = curr_cflags(cpu);
if (check_for_breakpoints(cpu, s.pc, &s.cflags)) {
cpu_loop_exit(cpu); cpu_loop_exit(cpu);
} }
tb = tb_lookup(cpu, pc, cs_base, flags, cflags); tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags);
if (tb == NULL) { if (tb == NULL) {
return tcg_code_gen_epilogue; return tcg_code_gen_epilogue;
} }
if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
log_cpu_exec(pc, cpu, tb); log_cpu_exec(s.pc, cpu, tb);
} }
return tb->tc.ptr; return tb->tc.ptr;
@ -560,11 +558,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu)
void cpu_exec_step_atomic(CPUState *cpu) void cpu_exec_step_atomic(CPUState *cpu)
{ {
CPUArchState *env = cpu_env(cpu);
TranslationBlock *tb; TranslationBlock *tb;
vaddr pc;
uint64_t cs_base;
uint32_t flags, cflags;
int tb_exit; int tb_exit;
if (sigsetjmp(cpu->jmp_env, 0) == 0) { if (sigsetjmp(cpu->jmp_env, 0) == 0) {
@ -573,13 +567,13 @@ void cpu_exec_step_atomic(CPUState *cpu)
g_assert(!cpu->running); g_assert(!cpu->running);
cpu->running = true; cpu->running = true;
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); TCGTBCPUState s = cpu_get_tb_cpu_state(cpu);
s.cflags = curr_cflags(cpu);
cflags = curr_cflags(cpu);
/* Execute in a serial context. */ /* Execute in a serial context. */
cflags &= ~CF_PARALLEL; s.cflags &= ~CF_PARALLEL;
/* After 1 insn, return and release the exclusive lock. */ /* After 1 insn, return and release the exclusive lock. */
cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; s.cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1;
/* /*
* No need to check_for_breakpoints here. * No need to check_for_breakpoints here.
* We only arrive in cpu_exec_step_atomic after beginning execution * We only arrive in cpu_exec_step_atomic after beginning execution
@ -587,16 +581,16 @@ void cpu_exec_step_atomic(CPUState *cpu)
* Any breakpoint for this insn will have been recognized earlier. * Any breakpoint for this insn will have been recognized earlier.
*/ */
tb = tb_lookup(cpu, pc, cs_base, flags, cflags); tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags);
if (tb == NULL) { if (tb == NULL) {
mmap_lock(); mmap_lock();
tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags);
mmap_unlock(); mmap_unlock();
} }
cpu_exec_enter(cpu); cpu_exec_enter(cpu);
/* execute the generated code */ /* execute the generated code */
trace_exec_tb(tb, pc); trace_exec_tb(tb, s.pc);
cpu_tb_exec(cpu, tb, &tb_exit); cpu_tb_exec(cpu, tb, &tb_exit);
cpu_exec_exit(cpu); cpu_exec_exit(cpu);
} else { } else {
@ -941,11 +935,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
while (!cpu_handle_interrupt(cpu, &last_tb)) { while (!cpu_handle_interrupt(cpu, &last_tb)) {
TranslationBlock *tb; TranslationBlock *tb;
vaddr pc; TCGTBCPUState s = cpu_get_tb_cpu_state(cpu);
uint64_t cs_base; s.cflags = cpu->cflags_next_tb;
uint32_t flags, cflags;
cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags);
/* /*
* When requested, use an exact setting for cflags for the next * When requested, use an exact setting for cflags for the next
@ -954,33 +945,32 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
* have CF_INVALID set, -1 is a convenient invalid value that * have CF_INVALID set, -1 is a convenient invalid value that
* does not require tcg headers for cpu_common_reset. * does not require tcg headers for cpu_common_reset.
*/ */
cflags = cpu->cflags_next_tb; if (s.cflags == -1) {
if (cflags == -1) { s.cflags = curr_cflags(cpu);
cflags = curr_cflags(cpu);
} else { } else {
cpu->cflags_next_tb = -1; cpu->cflags_next_tb = -1;
} }
if (check_for_breakpoints(cpu, pc, &cflags)) { if (check_for_breakpoints(cpu, s.pc, &s.cflags)) {
break; break;
} }
tb = tb_lookup(cpu, pc, cs_base, flags, cflags); tb = tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags);
if (tb == NULL) { if (tb == NULL) {
CPUJumpCache *jc; CPUJumpCache *jc;
uint32_t h; uint32_t h;
mmap_lock(); mmap_lock();
tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); tb = tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags);
mmap_unlock(); mmap_unlock();
/* /*
* We add the TB in the virtual pc hash table * We add the TB in the virtual pc hash table
* for the fast lookup * for the fast lookup
*/ */
h = tb_jmp_cache_hash_func(pc); h = tb_jmp_cache_hash_func(s.pc);
jc = cpu->tb_jmp_cache; jc = cpu->tb_jmp_cache;
jc->array[h].pc = pc; jc->array[h].pc = s.pc;
qatomic_set(&jc->array[h].tb, tb); qatomic_set(&jc->array[h].tb, tb);
} }
@ -1000,7 +990,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
tb_add_jump(last_tb, tb_exit, tb); tb_add_jump(last_tb, tb_exit, tb);
} }
cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit);
/* Try to align the host and virtual clocks /* Try to align the host and virtual clocks
if the guest is in advance */ if the guest is in advance */

8
accel/tcg/translate-all.c
View file

@ -590,13 +590,9 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
/* The exception probably happened in a helper. The CPU state should /* The exception probably happened in a helper. The CPU state should
have been saved before calling it. Fetch the PC from there. */ have been saved before calling it. Fetch the PC from there. */
CPUArchState *env = cpu_env(cpu); CPUArchState *env = cpu_env(cpu);
vaddr pc; TCGTBCPUState s = cpu_get_tb_cpu_state(cpu);
uint64_t cs_base; tb_page_addr_t addr = get_page_addr_code(env, s.pc);
tb_page_addr_t addr;
uint32_t flags;
cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
addr = get_page_addr_code(env, pc);
if (addr != -1) { if (addr != -1) {
tb_invalidate_phys_range(cpu, addr, addr); tb_invalidate_phys_range(cpu, addr, addr);
} }

4
include/accel/tcg/cpu-ops.h
View file

@ -16,10 +16,10 @@
#include "exec/memop.h" #include "exec/memop.h"
#include "exec/mmu-access-type.h" #include "exec/mmu-access-type.h"
#include "exec/vaddr.h" #include "exec/vaddr.h"
#include "accel/tcg/tb-cpu-state.h"
#include "tcg/tcg-mo.h" #include "tcg/tcg-mo.h"
void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs);
uint64_t *cs_base, uint32_t *flags);
struct TCGCPUOps { struct TCGCPUOps {
/** /**

18
include/accel/tcg/tb-cpu-state.h Normal file
View file

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: LGPL-2.1-or-later */
/*
* Definition of TCGTBCPUState.
*/
#ifndef EXEC_TB_CPU_STATE_H
#define EXEC_TB_CPU_STATE_H
#include "exec/vaddr.h"
typedef struct TCGTBCPUState {
vaddr pc;
uint32_t flags;
uint32_t cflags;
uint64_t cs_base;
} TCGTBCPUState;
#endif

13
target/alpha/cpu.c
View file

@ -41,15 +41,16 @@ static vaddr alpha_cpu_get_pc(CPUState *cs)
return env->pc; return env->pc;
} }
void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *pflags)
{ {
*pc = env->pc; CPUAlphaState *env = cpu_env(cs);
*cs_base = 0; uint32_t flags = env->flags & ENV_FLAG_TB_MASK;
*pflags = env->flags & ENV_FLAG_TB_MASK;
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
*pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus;
#endif #endif
return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
} }
static void alpha_cpu_synchronize_from_tb(CPUState *cs, static void alpha_cpu_synchronize_from_tb(CPUState *cs,

17
target/arm/tcg/hflags.c
View file

@ -10,6 +10,7 @@
#include "internals.h" #include "internals.h"
#include "cpu-features.h" #include "cpu-features.h"
#include "exec/helper-proto.h" #include "exec/helper-proto.h"
#include "exec/translation-block.h"
#include "accel/tcg/cpu-ops.h" #include "accel/tcg/cpu-ops.h"
#include "cpregs.h" #include "cpregs.h"
@ -544,21 +545,22 @@ static bool mve_no_pred(CPUARMState *env)
return true; return true;
} }
void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *pflags)
{ {
CPUARMState *env = cpu_env(cs);
CPUARMTBFlags flags; CPUARMTBFlags flags;
vaddr pc;
assert_hflags_rebuild_correctly(env); assert_hflags_rebuild_correctly(env);
flags = env->hflags; flags = env->hflags;
if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
*pc = env->pc; pc = env->pc;
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
DP_TBFLAG_A64(flags, BTYPE, env->btype); DP_TBFLAG_A64(flags, BTYPE, env->btype);
} }
} else { } else {
*pc = env->regs[15]; pc = env->regs[15];
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
if (arm_feature(env, ARM_FEATURE_M_SECURITY) && if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
@ -620,6 +622,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
DP_TBFLAG_ANY(flags, PSTATE__SS, 1); DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
} }
*pflags = flags.flags; return (TCGTBCPUState){
*cs_base = flags.flags2; .pc = pc,
.flags = flags.flags,
.cs_base = flags.flags2,
};
} }

9
target/avr/cpu.c
View file

@ -54,14 +54,11 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
} }
void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *pflags)
{ {
CPUAVRState *env = cpu_env(cs);
uint32_t flags = 0; uint32_t flags = 0;
*pc = env->pc_w * 2;
*cs_base = 0;
if (env->fullacc) { if (env->fullacc) {
flags |= TB_FLAGS_FULL_ACCESS; flags |= TB_FLAGS_FULL_ACCESS;
} }
@ -69,7 +66,7 @@ void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
flags |= TB_FLAGS_SKIP; flags |= TB_FLAGS_SKIP;
} }
*pflags = flags; return (TCGTBCPUState){ .pc = env->pc_w * 2, .flags = flags };
} }
static void avr_cpu_synchronize_from_tb(CPUState *cs, static void avr_cpu_synchronize_from_tb(CPUState *cs,

15
target/hexagon/cpu.c
View file

@ -255,19 +255,20 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs)
return cpu_env(cs)->gpr[HEX_REG_PC]; return cpu_env(cs)->gpr[HEX_REG_PC];
} }
void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
CPUHexagonState *env = cpu_env(cs);
vaddr pc = env->gpr[HEX_REG_PC];
uint32_t hex_flags = 0; uint32_t hex_flags = 0;
*pc = env->gpr[HEX_REG_PC];
*cs_base = 0; if (pc == env->gpr[HEX_REG_SA0]) {
if (*pc == env->gpr[HEX_REG_SA0]) {
hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
} }
*flags = hex_flags; if (pc & PCALIGN_MASK) {
if (*pc & PCALIGN_MASK) {
hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);
} }
return (TCGTBCPUState){ .pc = pc, .flags = hex_flags };
} }
static void hexagon_cpu_synchronize_from_tb(CPUState *cs, static void hexagon_cpu_synchronize_from_tb(CPUState *cs,

10
target/hppa/cpu.c
View file

@ -51,11 +51,12 @@ static vaddr hppa_cpu_get_pc(CPUState *cs)
env->iaoq_f & -4); env->iaoq_f & -4);
} }
void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *pcsbase, uint32_t *pflags)
{ {
CPUHPPAState *env = cpu_env(cs);
uint32_t flags = 0; uint32_t flags = 0;
uint64_t cs_base = 0; uint64_t cs_base = 0;
vaddr pc;
/* /*
* TB lookup assumes that PC contains the complete virtual address. * TB lookup assumes that PC contains the complete virtual address.
@ -63,7 +64,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
* incomplete virtual address. This also means that we must separate * incomplete virtual address. This also means that we must separate
* out current cpu privilege from the low bits of IAOQ_F. * out current cpu privilege from the low bits of IAOQ_F.
*/ */
*pc = hppa_cpu_get_pc(env_cpu(env)); pc = hppa_cpu_get_pc(env_cpu(env));
flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
/* /*
@ -99,8 +100,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
} }
#endif #endif
*pcsbase = cs_base; return (TCGTBCPUState){ .pc = pc, .flags = flags, .cs_base = cs_base };
*pflags = flags;
} }
static void hppa_cpu_synchronize_from_tb(CPUState *cs, static void hppa_cpu_synchronize_from_tb(CPUState *cs,

19
target/i386/tcg/tcg-cpu.c
View file

@ -48,18 +48,23 @@ static void x86_cpu_exec_exit(CPUState *cs)
env->eflags = cpu_compute_eflags(env); env->eflags = cpu_compute_eflags(env);
} }
void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*flags = env->hflags | CPUX86State *env = cpu_env(cs);
uint32_t flags, cs_base;
vaddr pc;
flags = env->hflags |
(env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
if (env->hflags & HF_CS64_MASK) { if (env->hflags & HF_CS64_MASK) {
*cs_base = 0; cs_base = 0;
*pc = env->eip; pc = env->eip;
} else { } else {
*cs_base = env->segs[R_CS].base; cs_base = env->segs[R_CS].base;
*pc = (uint32_t)(*cs_base + env->eip); pc = (uint32_t)(cs_base + env->eip);
} }
return (TCGTBCPUState){ .pc = pc, .flags = flags, .cs_base = cs_base };
} }
static void x86_cpu_synchronize_from_tb(CPUState *cs, static void x86_cpu_synchronize_from_tb(CPUState *cs,

20
target/loongarch/cpu.c
View file

@ -336,16 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
} }
#endif #endif
void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPULoongArchState *env = cpu_env(cs);
*cs_base = 0; uint32_t flags;
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
*flags |= is_va32(env) * HW_FLAGS_VA32; flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
flags |= is_va32(env) * HW_FLAGS_VA32;
return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
} }
static void loongarch_cpu_synchronize_from_tb(CPUState *cs, static void loongarch_cpu_synchronize_from_tb(CPUState *cs,

21
target/m68k/cpu.c
View file

@ -23,6 +23,7 @@
#include "cpu.h" #include "cpu.h"
#include "migration/vmstate.h" #include "migration/vmstate.h"
#include "fpu/softfloat.h" #include "fpu/softfloat.h"
#include "exec/translation-block.h"
#include "accel/tcg/cpu-ops.h" #include "accel/tcg/cpu-ops.h"
static void m68k_cpu_set_pc(CPUState *cs, vaddr value) static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
@ -39,20 +40,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs)
return cpu->env.pc; return cpu->env.pc;
} }
void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPUM68KState *env = cpu_env(cs);
*cs_base = 0; uint32_t flags;
*flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
if (env->sr & SR_S) { if (env->sr & SR_S) {
*flags |= TB_FLAGS_MSR_S; flags |= TB_FLAGS_MSR_S;
*flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
*flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
} }
if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
*flags |= TB_FLAGS_TRACE; flags |= TB_FLAGS_TRACE;
} }
return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
} }
static void m68k_restore_state_to_opc(CPUState *cs, static void m68k_restore_state_to_opc(CPUState *cs,

13
target/microblaze/cpu.c
View file

@ -95,12 +95,15 @@ static vaddr mb_cpu_get_pc(CPUState *cs)
return cpu->env.pc; return cpu->env.pc;
} }
void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPUMBState *env = cpu_env(cs);
*flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
*cs_base = (*flags & IMM_FLAG ? env->imm : 0); return (TCGTBCPUState){
.pc = env->pc,
.flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK),
.cs_base = (env->iflags & IMM_FLAG ? env->imm : 0),
};
} }
static void mb_cpu_synchronize_from_tb(CPUState *cs, static void mb_cpu_synchronize_from_tb(CPUState *cs,

14
target/mips/cpu.c
View file

@ -549,13 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
return mips_env_mmu_index(cpu_env(cs)); return mips_env_mmu_index(cpu_env(cs));
} }
void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->active_tc.PC; CPUMIPSState *env = cpu_env(cs);
*cs_base = 0;
*flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | return (TCGTBCPUState){
MIPS_HFLAG_HWRENA_ULR); .pc = env->active_tc.PC,
.flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
MIPS_HFLAG_HWRENA_ULR),
};
} }
static const TCGCPUOps mips_tcg_ops = { static const TCGCPUOps mips_tcg_ops = {

16
target/openrisc/cpu.c
View file

@ -41,14 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs)
return cpu->env.pc; return cpu->env.pc;
} }
void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPUOpenRISCState *env = cpu_env(cs);
*cs_base = 0;
*flags = (env->dflag ? TB_FLAGS_DFLAG : 0) return (TCGTBCPUState){
| (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) .pc = env->pc,
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); .flags = ((env->dflag ? TB_FLAGS_DFLAG : 0)
| (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))),
};
} }
static void openrisc_cpu_synchronize_from_tb(CPUState *cs, static void openrisc_cpu_synchronize_from_tb(CPUState *cs,

8
target/ppc/helper_regs.c
View file

@ -256,9 +256,9 @@ void hreg_update_pmu_hflags(CPUPPCState *env)
env->hflags |= hreg_compute_pmu_hflags_value(env); env->hflags |= hreg_compute_pmu_hflags_value(env);
} }
void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
CPUPPCState *env = cpu_env(cs);
uint32_t hflags_current = env->hflags; uint32_t hflags_current = env->hflags;
#ifdef CONFIG_DEBUG_TCG #ifdef CONFIG_DEBUG_TCG
@ -270,9 +270,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
} }
#endif #endif
*pc = env->nip; return (TCGTBCPUState){ .pc = env->nip, .flags = hflags_current };
*cs_base = 0;
*flags = hflags_current;
} }
void cpu_interrupt_exittb(CPUState *cs) void cpu_interrupt_exittb(CPUState *cs)

12
target/riscv/tcg/tcg-cpu.c
View file

@ -98,17 +98,14 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
return riscv_env_mmu_index(cpu_env(cs), ifetch); return riscv_env_mmu_index(cpu_env(cs), ifetch);
} }
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *pflags)
{ {
CPURISCVState *env = cpu_env(cs);
RISCVCPU *cpu = env_archcpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVExtStatus fs, vs; RISCVExtStatus fs, vs;
uint32_t flags = 0; uint32_t flags = 0;
bool pm_signext = riscv_cpu_virt_mem_enabled(env); bool pm_signext = riscv_cpu_virt_mem_enabled(env);
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
if (cpu->cfg.ext_zve32x) { if (cpu->cfg.ext_zve32x) {
/* /*
* If env->vl equals to VLMAX, we can use generic vector operation * If env->vl equals to VLMAX, we can use generic vector operation
@ -192,7 +189,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
*pflags = flags; return (TCGTBCPUState){
.pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,
.flags = flags
};
} }
static void riscv_cpu_synchronize_from_tb(CPUState *cs, static void riscv_cpu_synchronize_from_tb(CPUState *cs,

14
target/rx/cpu.c
View file

@ -44,13 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs)
return cpu->env.pc; return cpu->env.pc;
} }
void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPURXState *env = cpu_env(cs);
*cs_base = 0; uint32_t flags = 0;
*flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
*flags = FIELD_DP32(*flags, PSW, U, env->psw_u); flags = FIELD_DP32(flags, PSW, PM, env->psw_pm);
flags = FIELD_DP32(flags, PSW, U, env->psw_u);
return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
} }
static void rx_cpu_synchronize_from_tb(CPUState *cs, static void rx_cpu_synchronize_from_tb(CPUState *cs,

14
target/s390x/cpu.c
View file

@ -309,9 +309,9 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch)
return s390x_env_mmu_index(cpu_env(cs), ifetch); return s390x_env_mmu_index(cpu_env(cs), ifetch);
} }
void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *pflags)
{ {
CPUS390XState *env = cpu_env(cs);
uint32_t flags; uint32_t flags;
if (env->psw.addr & 1) { if (env->psw.addr & 1) {
@ -323,9 +323,6 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
} }
*pc = env->psw.addr;
*cs_base = env->ex_value;
flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
if (env->psw.mask & PSW_MASK_PER) { if (env->psw.mask & PSW_MASK_PER) {
flags |= env->cregs[9] & (FLAG_MASK_PER_BRANCH | flags |= env->cregs[9] & (FLAG_MASK_PER_BRANCH |
@ -342,7 +339,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
if (env->cregs[0] & CR0_VECTOR) { if (env->cregs[0] & CR0_VECTOR) {
flags |= FLAG_MASK_VECTOR; flags |= FLAG_MASK_VECTOR;
} }
*pflags = flags;
return (TCGTBCPUState){
.pc = env->psw.addr,
.flags = flags,
.cs_base = env->ex_value,
};
} }
static const TCGCPUOps s390_tcg_ops = { static const TCGCPUOps s390_tcg_ops = {

22
target/sh4/cpu.c
View file

@ -43,19 +43,27 @@ static vaddr superh_cpu_get_pc(CPUState *cs)
return cpu->env.pc; return cpu->env.pc;
} }
void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPUSH4State *env = cpu_env(cs);
/* For a gUSA region, notice the end of the region. */ uint32_t flags;
*cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
*flags = env->flags flags = env->flags
| (env->fpscr & TB_FLAG_FPSCR_MASK) | (env->fpscr & TB_FLAG_FPSCR_MASK)
| (env->sr & TB_FLAG_SR_MASK) | (env->sr & TB_FLAG_SR_MASK)
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
*flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus;
#endif #endif
return (TCGTBCPUState){
.pc = env->pc,
.flags = flags,
#ifdef CONFIG_USER_ONLY
/* For a gUSA region, notice the end of the region. */
.cs_base = flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0,
#endif
};
} }
static void superh_cpu_synchronize_from_tb(CPUState *cs, static void superh_cpu_synchronize_from_tb(CPUState *cs,

17
target/sparc/cpu.c
View file

@ -716,13 +716,11 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
cpu->env.npc = tb->cs_base; cpu->env.npc = tb->cs_base;
} }
void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *pflags)
{ {
uint32_t flags; CPUSPARCState *env = cpu_env(cs);
*pc = env->pc; uint32_t flags = cpu_mmu_index(cs, false);
*cs_base = env->npc;
flags = cpu_mmu_index(env_cpu(env), false);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (cpu_supervisor_mode(env)) { if (cpu_supervisor_mode(env)) {
flags |= TB_FLAG_SUPER; flags |= TB_FLAG_SUPER;
@ -751,7 +749,12 @@ void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
} }
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */
#endif /* TARGET_SPARC64 */ #endif /* TARGET_SPARC64 */
*pflags = flags;
return (TCGTBCPUState){
.pc = env->pc,
.flags = flags,
.cs_base = env->npc,
};
} }
static void sparc_restore_state_to_opc(CPUState *cs, static void sparc_restore_state_to_opc(CPUState *cs,

14
target/tricore/cpu.c
View file

@ -45,16 +45,14 @@ static vaddr tricore_cpu_get_pc(CPUState *cs)
return cpu_env(cs)->PC; return cpu_env(cs)->PC;
} }
void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
uint32_t new_flags = 0; CPUTriCoreState *env = cpu_env(cs);
*pc = env->PC;
*cs_base = 0;
new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, return (TCGTBCPUState){
extract32(env->PSW, 10, 2)); .pc = env->PC,
*flags = new_flags; .flags = FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2)),
};
} }
static void tricore_cpu_synchronize_from_tb(CPUState *cs, static void tricore_cpu_synchronize_from_tb(CPUState *cs,

40
target/xtensa/cpu.c
View file

@ -55,15 +55,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs)
return cpu->env.pc; return cpu->env.pc;
} }
void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs)
uint64_t *cs_base, uint32_t *flags)
{ {
*pc = env->pc; CPUXtensaState *env = cpu_env(cs);
*cs_base = 0; uint32_t flags = 0;
*flags = 0; target_ulong cs_base = 0;
*flags |= xtensa_get_ring(env);
flags |= xtensa_get_ring(env);
if (env->sregs[PS] & PS_EXCM) { if (env->sregs[PS] & PS_EXCM) {
*flags |= XTENSA_TBFLAG_EXCM; flags |= XTENSA_TBFLAG_EXCM;
} else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
target_ulong lend_dist = target_ulong lend_dist =
env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
@ -85,26 +85,26 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
*cs_base = lend_dist; cs_base = lend_dist;
if (lbeg_off < 256) { if (lbeg_off < 256) {
*cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
} }
} }
} }
if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
(env->sregs[LITBASE] & 1)) { (env->sregs[LITBASE] & 1)) {
*flags |= XTENSA_TBFLAG_LITBASE; flags |= XTENSA_TBFLAG_LITBASE;
} }
if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
if (xtensa_get_cintlevel(env) < env->config->debug_level) { if (xtensa_get_cintlevel(env) < env->config->debug_level) {
*flags |= XTENSA_TBFLAG_DEBUG; flags |= XTENSA_TBFLAG_DEBUG;
} }
if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
*flags |= XTENSA_TBFLAG_ICOUNT; flags |= XTENSA_TBFLAG_ICOUNT;
} }
} }
if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
*flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
} }
if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
(env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
@ -112,15 +112,21 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
(env->sregs[WINDOW_BASE] + 1); (env->sregs[WINDOW_BASE] + 1);
uint32_t w = ctz32(windowstart | 0x8); uint32_t w = ctz32(windowstart | 0x8);
*flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
*flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
} else { } else {
*flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
} }
if (env->yield_needed) { if (env->yield_needed) {
*flags |= XTENSA_TBFLAG_YIELD; flags |= XTENSA_TBFLAG_YIELD;
} }
return (TCGTBCPUState){
.pc = env->pc,
.flags = flags,
.cs_base = cs_base,
};
} }
static void xtensa_restore_state_to_opc(CPUState *cs, static void xtensa_restore_state_to_opc(CPUState *cs,