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https://github.com/Motorhead1991/qemu.git
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target/ppc: moved ppc_cpu_dump_state to cpu_init.c
This function was forgotten in the cpu_init code motion series, but it seems to be used regardless of TCG, and so needs to be moved to support disabling TCG. Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210512140813.112884-4-bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai)
David Gibson
parent
172d74efda
commit
47334e1738
2 changed files with 182 additions and 187 deletions
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@ -9368,4 +9368,186 @@ static void ppc_cpu_register_types(void)
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#endif
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#endif
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}
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}
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void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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#define RGPL 4
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#define RFPL 4
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int i;
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qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
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TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
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env->nip, env->lr, env->ctr, cpu_read_xer(env),
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cs->cpu_index);
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qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
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"%08x iidx %d didx %d\n",
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env->msr, env->spr[SPR_HID0], env->hflags,
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cpu_mmu_index(env, true), cpu_mmu_index(env, false));
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#if !defined(NO_TIMER_DUMP)
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qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
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#if !defined(CONFIG_USER_ONLY)
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" DECR " TARGET_FMT_lu
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#endif
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"\n",
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cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
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#if !defined(CONFIG_USER_ONLY)
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, cpu_ppc_load_decr(env)
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#endif
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);
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#endif
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for (i = 0; i < 32; i++) {
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if ((i & (RGPL - 1)) == 0) {
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qemu_fprintf(f, "GPR%02d", i);
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}
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qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
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if ((i & (RGPL - 1)) == (RGPL - 1)) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "CR ");
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for (i = 0; i < 8; i++)
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qemu_fprintf(f, "%01x", env->crf[i]);
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qemu_fprintf(f, " [");
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for (i = 0; i < 8; i++) {
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char a = '-';
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if (env->crf[i] & 0x08) {
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a = 'L';
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} else if (env->crf[i] & 0x04) {
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a = 'G';
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} else if (env->crf[i] & 0x02) {
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a = 'E';
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}
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qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
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}
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qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
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env->reserve_addr);
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if (flags & CPU_DUMP_FPU) {
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for (i = 0; i < 32; i++) {
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if ((i & (RFPL - 1)) == 0) {
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qemu_fprintf(f, "FPR%02d", i);
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}
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qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
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if ((i & (RFPL - 1)) == (RFPL - 1)) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
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}
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#if !defined(CONFIG_USER_ONLY)
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qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
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" PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
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env->spr[SPR_SRR0], env->spr[SPR_SRR1],
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env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
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qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
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" SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
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env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
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env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
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qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
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" SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
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env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
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env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
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#if defined(TARGET_PPC64)
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if (env->excp_model == POWERPC_EXCP_POWER7 ||
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env->excp_model == POWERPC_EXCP_POWER8 ||
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env->excp_model == POWERPC_EXCP_POWER9 ||
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env->excp_model == POWERPC_EXCP_POWER10) {
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qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
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env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
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}
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#endif
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if (env->excp_model == POWERPC_EXCP_BOOKE) {
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qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
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" MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
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env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
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env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
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qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
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" ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
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env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
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env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
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qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
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" IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
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env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
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env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
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qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
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" EPR " TARGET_FMT_lx "\n",
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env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
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env->spr[SPR_BOOKE_EPR]);
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/* FSL-specific */
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qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
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" PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
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env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
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env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
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/*
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* IVORs are left out as they are large and do not change often --
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* they can be read with "p $ivor0", "p $ivor1", etc.
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*/
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}
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#if defined(TARGET_PPC64)
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if (env->flags & POWERPC_FLAG_CFAR) {
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qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
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}
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#endif
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if (env->spr_cb[SPR_LPCR].name) {
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qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
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}
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switch (env->mmu_model) {
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case POWERPC_MMU_32B:
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case POWERPC_MMU_601:
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case POWERPC_MMU_SOFT_6xx:
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case POWERPC_MMU_SOFT_74xx:
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#if defined(TARGET_PPC64)
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case POWERPC_MMU_64B:
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case POWERPC_MMU_2_03:
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case POWERPC_MMU_2_06:
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case POWERPC_MMU_2_07:
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case POWERPC_MMU_3_00:
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#endif
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if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
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qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
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}
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if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
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qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
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}
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qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
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env->spr[SPR_DAR], env->spr[SPR_DSISR]);
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break;
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case POWERPC_MMU_BOOKE206:
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qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
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" MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
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env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
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env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
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qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
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" MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
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env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
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env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
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qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
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" TLB1CFG " TARGET_FMT_lx "\n",
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env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
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env->spr[SPR_BOOKE_TLB1CFG]);
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break;
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default:
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break;
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}
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#endif
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#undef RGPL
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#undef RFPL
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}
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type_init(ppc_cpu_register_types)
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type_init(ppc_cpu_register_types)
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@ -8617,193 +8617,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
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#include "translate/spe-ops.c.inc"
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#include "translate/spe-ops.c.inc"
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};
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};
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#include "helper_regs.h"
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/*****************************************************************************/
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/* Misc PowerPC helpers */
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void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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#define RGPL 4
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#define RFPL 4
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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int i;
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qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
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TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
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env->nip, env->lr, env->ctr, cpu_read_xer(env),
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cs->cpu_index);
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qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
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"%08x iidx %d didx %d\n",
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env->msr, env->spr[SPR_HID0], env->hflags,
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cpu_mmu_index(env, true), cpu_mmu_index(env, false));
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#if !defined(NO_TIMER_DUMP)
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qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
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#if !defined(CONFIG_USER_ONLY)
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" DECR " TARGET_FMT_lu
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#endif
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"\n",
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cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
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#if !defined(CONFIG_USER_ONLY)
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, cpu_ppc_load_decr(env)
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#endif
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);
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#endif
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for (i = 0; i < 32; i++) {
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if ((i & (RGPL - 1)) == 0) {
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qemu_fprintf(f, "GPR%02d", i);
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}
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qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
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if ((i & (RGPL - 1)) == (RGPL - 1)) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "CR ");
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for (i = 0; i < 8; i++)
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qemu_fprintf(f, "%01x", env->crf[i]);
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qemu_fprintf(f, " [");
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for (i = 0; i < 8; i++) {
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char a = '-';
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if (env->crf[i] & 0x08) {
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a = 'L';
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} else if (env->crf[i] & 0x04) {
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a = 'G';
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} else if (env->crf[i] & 0x02) {
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a = 'E';
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}
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qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
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}
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qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
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env->reserve_addr);
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if (flags & CPU_DUMP_FPU) {
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for (i = 0; i < 32; i++) {
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if ((i & (RFPL - 1)) == 0) {
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qemu_fprintf(f, "FPR%02d", i);
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}
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qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
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if ((i & (RFPL - 1)) == (RFPL - 1)) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
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}
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#if !defined(CONFIG_USER_ONLY)
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qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
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" PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
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env->spr[SPR_SRR0], env->spr[SPR_SRR1],
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env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
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qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
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" SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
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env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
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env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
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qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
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" SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
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env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
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env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
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#if defined(TARGET_PPC64)
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if (env->excp_model == POWERPC_EXCP_POWER7 ||
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env->excp_model == POWERPC_EXCP_POWER8 ||
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env->excp_model == POWERPC_EXCP_POWER9 ||
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env->excp_model == POWERPC_EXCP_POWER10) {
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qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
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env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
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}
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#endif
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if (env->excp_model == POWERPC_EXCP_BOOKE) {
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qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
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|
||||||
" MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
|
|
||||||
env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
|
|
||||||
|
|
||||||
qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
|
|
||||||
" ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
|
|
||||||
env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
|
|
||||||
|
|
||||||
qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
|
|
||||||
" IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
|
|
||||||
env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
|
|
||||||
|
|
||||||
qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
|
|
||||||
" EPR " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
|
|
||||||
env->spr[SPR_BOOKE_EPR]);
|
|
||||||
|
|
||||||
/* FSL-specific */
|
|
||||||
qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
|
|
||||||
" PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
|
|
||||||
env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IVORs are left out as they are large and do not change often --
|
|
||||||
* they can be read with "p $ivor0", "p $ivor1", etc.
|
|
||||||
*/
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(TARGET_PPC64)
|
|
||||||
if (env->flags & POWERPC_FLAG_CFAR) {
|
|
||||||
qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (env->spr_cb[SPR_LPCR].name) {
|
|
||||||
qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (env->mmu_model) {
|
|
||||||
case POWERPC_MMU_32B:
|
|
||||||
case POWERPC_MMU_601:
|
|
||||||
case POWERPC_MMU_SOFT_6xx:
|
|
||||||
case POWERPC_MMU_SOFT_74xx:
|
|
||||||
#if defined(TARGET_PPC64)
|
|
||||||
case POWERPC_MMU_64B:
|
|
||||||
case POWERPC_MMU_2_03:
|
|
||||||
case POWERPC_MMU_2_06:
|
|
||||||
case POWERPC_MMU_2_07:
|
|
||||||
case POWERPC_MMU_3_00:
|
|
||||||
#endif
|
|
||||||
if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
|
|
||||||
qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
|
|
||||||
}
|
|
||||||
if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
|
|
||||||
qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
|
|
||||||
}
|
|
||||||
qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_DAR], env->spr[SPR_DSISR]);
|
|
||||||
break;
|
|
||||||
case POWERPC_MMU_BOOKE206:
|
|
||||||
qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
|
|
||||||
" MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
|
|
||||||
env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
|
|
||||||
|
|
||||||
qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
|
|
||||||
" MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
|
|
||||||
env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
|
|
||||||
|
|
||||||
qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
|
|
||||||
" TLB1CFG " TARGET_FMT_lx "\n",
|
|
||||||
env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
|
|
||||||
env->spr[SPR_BOOKE_TLB1CFG]);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#undef RGPL
|
|
||||||
#undef RFPL
|
|
||||||
}
|
|
||||||
|
|
||||||
/*****************************************************************************/
|
/*****************************************************************************/
|
||||||
/* Opcode types */
|
/* Opcode types */
|
||||||
enum {
|
enum {
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue