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Hexagon (target/hexagon) circular addressing
The following instructions are added
L2_loadrub_pci Rd32 = memub(Rx32++#s4:0:circ(Mu2))
L2_loadrb_pci Rd32 = memb(Rx32++#s4:0:circ(Mu2))
L2_loadruh_pci Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
L2_loadrh_pci Rd32 = memh(Rx32++#s4:1:circ(Mu2))
L2_loadri_pci Rd32 = memw(Rx32++#s4:2:circ(Mu2))
L2_loadrd_pci Rdd32 = memd(Rx32++#s4:3:circ(Mu2))
S2_storerb_pci memb(Rx32++#s4:0:circ(Mu2)) = Rt32
S2_storerh_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt32
S2_storerf_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32
S2_storeri_pci memw(Rx32++#s4:2:circ(Mu2)) = Rt32
S2_storerd_pci memd(Rx32++#s4:3:circ(Mu2)) = Rtt32
S2_storerbnew_pci memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new
S2_storerhnew_pci memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new
S2_storerinew_pci memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new
L2_loadrub_pcr Rd32 = memub(Rx32++I:circ(Mu2))
L2_loadrb_pcr Rd32 = memb(Rx32++I:circ(Mu2))
L2_loadruh_pcr Rd32 = memuh(Rx32++I:circ(Mu2))
L2_loadrh_pcr Rd32 = memh(Rx32++I:circ(Mu2))
L2_loadri_pcr Rd32 = memw(Rx32++I:circ(Mu2))
L2_loadrd_pcr Rdd32 = memd(Rx32++I:circ(Mu2))
S2_storerb_pcr memb(Rx32++I:circ(Mu2)) = Rt32
S2_storerh_pcr memh(Rx32++I:circ(Mu2)) = Rt32
S2_storerf_pcr memh(Rx32++I:circ(Mu2)) = Rt32.H32
S2_storeri_pcr memw(Rx32++I:circ(Mu2)) = Rt32
S2_storerd_pcr memd(Rx32++I:circ(Mu2)) = Rtt32
S2_storerbnew_pcr memb(Rx32++I:circ(Mu2)) = Nt8.new
S2_storerhnew_pcr memh(Rx32++I:circ(Mu2)) = Nt8.new
S2_storerinew_pcr memw(Rx32++I:circ(Mu2)) = Nt8.new
Test cases in tests/tcg/hexagon/circ.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-23-git-send-email-tsimpson@quicinc.com>
[rth: Squash <1619667142-29636-1-git-send-email-tsimpson@quicinc.com>
removing gen_read_reg and gen_set_byte to avoid clang Werror.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson
Richard Henderson
parent
57d352ac29
commit
46ef47e2a7
9 changed files with 834 additions and 23 deletions
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@ -294,6 +294,7 @@ DEF_CLASS32(ICLASS_LD" ---- -------- PP------ --------",LD)
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DEF_CLASS32(ICLASS_LD" 0--- -------- PP------ --------",LD_ADDR_ROFFSET)
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DEF_CLASS32(ICLASS_LD" 100- -------- PP----0- --------",LD_ADDR_POST_CIRC_IMMED)
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DEF_CLASS32(ICLASS_LD" 101- -------- PP00---- --------",LD_ADDR_POST_IMMED)
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DEF_CLASS32(ICLASS_LD" 101- -------- PP01---- --------",LD_ADDR_ABS_UPDATE_V4)
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DEF_CLASS32(ICLASS_LD" 101- -------- PP1----- --------",LD_ADDR_POST_IMMED_PRED_V2)
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@ -308,18 +309,23 @@ DEF_FIELD32(ICLASS_LD" ---- --!----- PP------ --------",LD_UN,"Unsigned")
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#define STD_LD_ENC(TAG,OPC) \
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DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iiiddddd")\
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DEF_ENC32(L2_load##TAG##_pci, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--0i iiiddddd")\
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DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iiiddddd")\
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DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -IIddddd")\
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DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--ddddd")\
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DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iIIddddd")\
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DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--ddddd")\
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#define STD_LDX_ENC(TAG,OPC) \
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DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iiiyyyyy")\
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DEF_ENC32(L2_load##TAG##_pci, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--0i iiiyyyyy")\
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DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iiiyyyyy")\
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DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -IIyyyyy")\
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DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--yyyyy")\
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DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iIIyyyyy")\
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DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--yyyyy")\
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DEF_ENC32(L2_load##TAG##_pbr, ICLASS_LD" 1 11 "OPC" xxxxx PPu0---- 0--yyyyy")
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#define STD_PLD_ENC(TAG,OPC) \
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@ -351,6 +357,7 @@ STD_PLD_ENC(rd, "1 110") /* note dest reg field LSB=0, 1 is reserved */
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DEF_CLASS32( ICLASS_LD" 0--0 000----- PP------ --------",LD_MISC)
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DEF_ANTICLASS32(ICLASS_LD" 0--0 000----- PP------ --------",LD_ADDR_ROFFSET)
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DEF_ANTICLASS32(ICLASS_LD" 1000 000----- PP------ --------",LD_ADDR_POST_CIRC_IMMED)
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DEF_ANTICLASS32(ICLASS_LD" 1010 000----- PP------ --------",LD_ADDR_POST_IMMED)
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DEF_ANTICLASS32(ICLASS_LD" 1100 000----- PP------ --------",LD_ADDR_POST_REG)
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DEF_ANTICLASS32(ICLASS_LD" 1110 000----- PP------ --------",LD_ADDR_POST_REG)
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@ -397,6 +404,7 @@ DEF_FIELD32(ICLASS_ST" ---! !!------ PP------ --------",ST_Type,"Type")
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DEF_FIELD32(ICLASS_ST" ---- --!----- PP------ --------",ST_UN,"Unsigned")
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DEF_CLASS32(ICLASS_ST" 0--1 -------- PP------ --------",ST_ADDR_ROFFSET)
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DEF_CLASS32(ICLASS_ST" 1001 -------- PP------ ------0-",ST_ADDR_POST_CIRC_IMMED)
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DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 0-----0-",ST_ADDR_POST_IMMED)
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DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 1-------",ST_ADDR_ABS_UPDATE_V4)
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DEF_CLASS32(ICLASS_ST" 1011 -------- PP1----- --------",ST_ADDR_POST_IMMED_PRED_V2)
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@ -411,10 +419,12 @@ DEF_CLASS32(ICLASS_ST" 0--0 0------- PP------ --------",ST_MISC_CACHEOP)
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#define STD_ST_ENC(TAG,OPC,SRC) \
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DEF_ENC32(S2_store##TAG##_io, ICLASS_ST" 0 ii "OPC" sssss PPi"SRC" iiiiiiii")\
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DEF_ENC32(S2_store##TAG##_pci, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0iiii-0-")\
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DEF_ENC32(S2_store##TAG##_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP0"SRC" 0iiii-0-")\
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DEF_ENC32(S4_store##TAG##_ap, ICLASS_ST" 1 01 "OPC" eeeee PP0"SRC" 1-IIIIII")\
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DEF_ENC32(S2_store##TAG##_pr, ICLASS_ST" 1 10 "OPC" xxxxx PPu"SRC" 0-------")\
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DEF_ENC32(S4_store##TAG##_ur, ICLASS_ST" 1 10 "OPC" uuuuu PPi"SRC" 1iIIIIII")\
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DEF_ENC32(S2_store##TAG##_pcr, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0-----1-")\
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#define STD_PST_ENC(TAG,OPC,SRC) \
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@ -26,6 +26,8 @@ Q6INSN(L4_##TAG##_ur, OPER"(Rt32<<#u2+#U6)", ATTRIB,DESCR,{fMUST_IM
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Q6INSN(L4_##TAG##_ap, OPER"(Re32=#U6)", ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IMM(UiV); SEMANTICS; ReV=UiV; })\
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Q6INSN(L2_##TAG##_pr, OPER"(Rx32++Mu2)", ATTRIB,DESCR,{fEA_REG(RxV); fPM_M(RxV,MuV); SEMANTICS;})\
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Q6INSN(L2_##TAG##_pi, OPER"(Rx32++#s4:"SHFT")", ATTRIB,DESCR,{fEA_REG(RxV); fPM_I(RxV,siV); SEMANTICS;})\
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Q6INSN(L2_##TAG##_pci, OPER"(Rx32++#s4:"SHFT":circ(Mu2))",ATTRIB,DESCR,{fEA_REG(RxV); fPM_CIRI(RxV,siV,MuV); SEMANTICS;})\
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Q6INSN(L2_##TAG##_pcr, OPER"(Rx32++I:circ(Mu2))", ATTRIB,DESCR,{fEA_REG(RxV); fPM_CIRR(RxV,fREAD_IREG(MuV)<<SCALE,MuV); SEMANTICS;})
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/* The set of 32-bit load instructions */
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STD_LD_AMODES(loadrub,"Rd32=memub","Load Unsigned Byte",ATTRIBS(A_LOAD),"0",fLOAD(1,1,u,EA,RdV),0)
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@ -42,6 +44,8 @@ Q6INSN(S2_##TAG##_pi, OPER"(Rx32++#s4:"SHFT")="DEST, ATTRIB,DESCR,{fEA_REG(
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Q6INSN(S4_##TAG##_ap, OPER"(Re32=#U6)="DEST, ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IMM(UiV); SEMANTICS; ReV=UiV; })\
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Q6INSN(S2_##TAG##_pr, OPER"(Rx32++Mu2)="DEST, ATTRIB,DESCR,{fEA_REG(RxV); fPM_M(RxV,MuV); SEMANTICS; })\
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Q6INSN(S4_##TAG##_ur, OPER"(Ru32<<#u2+#U6)="DEST, ATTRIB,DESCR,{fMUST_IMMEXT(UiV); fEA_IRs(UiV,RuV,uiV); SEMANTICS;})\
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Q6INSN(S2_##TAG##_pci, OPER"(Rx32++#s4:"SHFT":circ(Mu2))="DEST, ATTRIB,DESCR,{fEA_REG(RxV); fPM_CIRI(RxV,siV,MuV); SEMANTICS;})\
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Q6INSN(S2_##TAG##_pcr, OPER"(Rx32++I:circ(Mu2))="DEST, ATTRIB,DESCR,{fEA_REG(RxV); fPM_CIRR(RxV,fREAD_IREG(MuV)<<SCALE,MuV); SEMANTICS;})
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/* The set of 32-bit store instructions */
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@ -276,6 +276,12 @@ DEF_MACRO(
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/* Read and Write Implicit Regs */
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/*************************************/
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DEF_MACRO(
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fREAD_IREG, /* read modifier register */
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(fSXTN(11,64,(((VAL) & 0xf0000000)>>21) | ((VAL>>17)&0x7f) )), /* behavior */
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()
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)
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DEF_MACRO(
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fREAD_LR, /* read link register */
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(READ_RREG(REG_LR)), /* behavior */
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@ -306,6 +312,12 @@ DEF_MACRO(
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()
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)
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DEF_MACRO(
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fREAD_CSREG, /* read CS register */
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(READ_RREG(REG_CSA+N)), /* behavior */
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()
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)
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DEF_MACRO(
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fREAD_LC0, /* read loop count */
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(READ_RREG(REG_LC0)), /* behavior */
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@ -824,6 +836,20 @@ DEF_MACRO(
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()
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)
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DEF_MACRO(
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fPM_CIRI, /* Post Modify Register using Circular arithmetic by Immediate */
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do { fcirc_add(REG,siV,MuV); } while (0),
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()
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)
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DEF_MACRO(
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fPM_CIRR, /* Post Modify Register using Circular arithmetic by register */
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do { fcirc_add(REG,VAL,MuV); } while (0),
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()
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)
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DEF_MACRO(
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fSCALE, /* scale by N */
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(((size8s_t)(A))<<N),
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