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hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block

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Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU-device support to the devinfo array handling code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:46:07 +00:00
parent f11de23158
commit 4668b441cb
2 changed files with 29 additions and 0 deletions
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3
include/hw/arm/armsse.h
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@ -104,6 +104,7 @@
#include "hw/misc/iotkit-sysinfo.h"
#include "hw/misc/armsse-cpuid.h"
#include "hw/misc/armsse-mhu.h"
#include "hw/misc/armsse-cpu-pwrctrl.h"
#include "hw/misc/unimp.h"
#include "hw/or-irq.h"
#include "hw/clock.h"
@ -179,6 +180,8 @@ struct ARMSSE {
ARMSSECPUID cpuid[SSE_MAX_CPUS];
ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS];
/*
* 'container' holds all devices seen by all CPUs.
* 'cpu_container[i]' is the view that CPU i has: this has the