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target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'

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Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2022-02-02 01:52:43 +01:00 • committed by Alistair Francis
parent 6c3a924725
commit 466292bd4a
1 changed files with 41 additions and 37 deletions
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78
target/riscv/cpu.h
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@ -303,6 +303,46 @@ struct RISCVCPUClass {
DeviceReset parent_reset; DeviceReset parent_reset;
}; };
struct RISCVCPUConfig {
bool ext_i;
bool ext_e;
bool ext_g;
bool ext_m;
bool ext_a;
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
bool ext_zbs;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zve32f;
bool ext_zve64f;
char *priv_spec;
char *user_spec;
char *bext_spec;
char *vext_spec;
uint16_t vlen;
uint16_t elen;
bool mmu;
bool pmp;
bool epmp;
uint64_t resetvec;
};
typedef struct RISCVCPUConfig RISCVCPUConfig;
/** /**
* RISCVCPU: * RISCVCPU:
* @env: #CPURISCVState * @env: #CPURISCVState
@ -320,43 +360,7 @@ struct RISCVCPU {
char *dyn_vreg_xml; char *dyn_vreg_xml;
/* Configuration Settings */ /* Configuration Settings */
struct { RISCVCPUConfig cfg;
bool ext_i;
bool ext_e;
bool ext_g;
bool ext_m;
bool ext_a;
bool ext_f;
bool ext_d;
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
bool ext_zbs;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zve32f;
bool ext_zve64f;
char *priv_spec;
char *user_spec;
char *bext_spec;
char *vext_spec;
uint16_t vlen;
uint16_t elen;
bool mmu;
bool pmp;
bool epmp;
uint64_t resetvec;
} cfg;
}; };
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)