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target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig'
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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1 changed files with 41 additions and 37 deletions
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@ -303,24 +303,7 @@ struct RISCVCPUClass {
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DeviceReset parent_reset;
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DeviceReset parent_reset;
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};
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};
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/**
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struct RISCVCPUConfig {
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* RISCVCPU:
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* @env: #CPURISCVState
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*
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* A RISCV CPU.
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*/
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struct RISCVCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPURISCVState env;
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char *dyn_csr_xml;
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char *dyn_vreg_xml;
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/* Configuration Settings */
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struct {
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bool ext_i;
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bool ext_i;
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bool ext_e;
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bool ext_e;
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bool ext_g;
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bool ext_g;
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@ -356,7 +339,28 @@ struct RISCVCPU {
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bool pmp;
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bool pmp;
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bool epmp;
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bool epmp;
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uint64_t resetvec;
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uint64_t resetvec;
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} cfg;
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};
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typedef struct RISCVCPUConfig RISCVCPUConfig;
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/**
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* RISCVCPU:
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* @env: #CPURISCVState
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*
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* A RISCV CPU.
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*/
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struct RISCVCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPURISCVState env;
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char *dyn_csr_xml;
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char *dyn_vreg_xml;
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/* Configuration Settings */
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RISCVCPUConfig cfg;
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};
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};
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
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