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RISC-V: Adding T-Head MemIdx extension

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This patch adds support for the T-Head MemIdx instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:08 +01:00 • committed by Alistair Francis
parent af99aa72ef
commit 45f9df86db
5 changed files with 464 additions and 1 deletions
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54
target/riscv/xthead.decode
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@ -17,8 +17,10 @@
%rd2 20:5
%rs2 20:5
%sh5 20:5
%imm5 20:s5
%sh6 20:6
%sh2 25:2
%imm2 25:2
# Argument sets
&r rd rs1 rs2 !extern
@ -26,6 +28,8 @@
&shift shamt rs1 rd !extern
&th_bfext msb lsb rs1 rd
&th_pair rd1 rs rd2 sh2
&th_memidx rd rs1 rs2 imm2
&th_meminc rd rs1 imm5 imm2
# Formats
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@ -36,6 +40,8 @@
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2
@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2
@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2
# XTheadBa
# Instead of defining a new encoding, we simply use the decoder to
@ -102,6 +108,54 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r
th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r
th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r
# XTheadMemIdx
th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc
th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc
th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc
th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc
th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc
th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc
th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc
th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc
th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc
th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc
th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc
th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx
th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx
th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx
th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx
th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx
th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx
th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx
th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx
th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx
th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx
th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx
# XTheadMemPair
th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair
th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair