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target/arm: Convert MSR (immediate) to decodetree

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Convert the MSR (immediate) insn to decodetree. Our implementation
has basically no commonality between the different destinations,
so we decode the destination register in a64.decode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-06-19 11:20:20 +01:00
parent d78b662f28
commit 45d063d163
2 changed files with 136 additions and 128 deletions
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13
target/arm/tcg/a64.decode
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@ -194,3 +194,16 @@ SB 1101 0101 0000 0011 0011 0000 111 11111
CFINV 1101 0101 0000 0 000 0100 0000 000 11111
XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111
AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111
# These are architecturally all "MSR (immediate)"; we decode the destination
# register too because there is no commonality in our implementation.
@msr_i .... .... .... . ... .... imm:4 ... .....
MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i
MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i
MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i
MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i
MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111