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target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op

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QEMU does not model caches, so there is not much to do with the
Invalidate/Writeback opcodes. Make it explicit adding a comment.

Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-3-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-08-13 19:49:22 +02:00
parent 4a367cfb00
commit 45964263e4
1 changed files with 5 additions and 0 deletions
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5
target/mips/op_helper.c
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@ -1586,6 +1586,11 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
MO_64, MEMTXATTRS_UNSPECIFIED); MO_64, MEMTXATTRS_UNSPECIFIED);
break; break;
case 0b000: /* Index Invalidate */
case 0b100: /* Hit Invalidate */
case 0b110: /* Hit Writeback */
/* no-op */
break;
default: default:
break; break;
} }