motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2026-01-06 06:27:41 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: rvv-1.0: add vcsr register

Browse source 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-10-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2021-12-10 15:55:55 +08:00 • committed by Alistair Francis
parent 9bd291f6e3
commit 4594fa5a96
2 changed files with 24 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target/riscv/cpu_bits.h
View file

@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
#define VCSR_VXRM_SHIFT 1
#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01