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target/openrisc: Merge tlb allocation into CPUOpenRISCState

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There is no reason to allocate this separately.  This was probably
copied from target/mips which makes the same mistake.

While doing so, move tlb into the clear-on-reset range.  While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Richard Henderson 2018-05-22 16:28:33 -07:00 • committed by Stafford Horne
parent c28fa81f91
commit 455d45d22c
6 changed files with 46 additions and 49 deletions
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34
target/openrisc/mmu.c
View file

@ -46,19 +46,19 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
int idx = vpn & ITLB_MASK;
int right = 0;
if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) {
if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
if (cpu->env.sr & SR_SM) { /* supervisor mode */
if (cpu->env.tlb->itlb[0][idx].tr & SXE) {
if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
right |= PAGE_EXEC;
}
} else {
if (cpu->env.tlb->itlb[0][idx].tr & UXE) {
if (cpu->env.tlb.itlb[0][idx].tr & UXE) {
right |= PAGE_EXEC;
}
}
@ -67,7 +67,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
return TLBRET_BADADDR;
}
*physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) |
*physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) |
(address & (TARGET_PAGE_SIZE-1));
*prot = right;
return TLBRET_MATCH;
@ -81,25 +81,25 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
int idx = vpn & DTLB_MASK;
int right = 0;
if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) {
if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
if (cpu->env.sr & SR_SM) { /* supervisor mode */
if (cpu->env.tlb->dtlb[0][idx].tr & SRE) {
if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
right |= PAGE_READ;
}
if (cpu->env.tlb->dtlb[0][idx].tr & SWE) {
if (cpu->env.tlb.dtlb[0][idx].tr & SWE) {
right |= PAGE_WRITE;
}
} else {
if (cpu->env.tlb->dtlb[0][idx].tr & URE) {
if (cpu->env.tlb.dtlb[0][idx].tr & URE) {
right |= PAGE_READ;
}
if (cpu->env.tlb->dtlb[0][idx].tr & UWE) {
if (cpu->env.tlb.dtlb[0][idx].tr & UWE) {
right |= PAGE_WRITE;
}
}
@ -111,7 +111,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
return TLBRET_BADADDR;
}
*physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) |
*physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) |
(address & (TARGET_PAGE_SIZE-1));
*prot = right;
return TLBRET_MATCH;
@ -126,10 +126,10 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
if (rw == MMU_INST_FETCH) { /* ITLB */
*physical = 0;
ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical,
prot, address, rw);
} else { /* DTLB */
ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical,
ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical,
prot, address, rw);
}
@ -247,9 +247,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
{
cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext));
cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
}
#endif