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target/openrisc: Merge tlb allocation into CPUOpenRISCState

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There is no reason to allocate this separately.  This was probably
copied from target/mips which makes the same mistake.

While doing so, move tlb into the clear-on-reset range.  While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Richard Henderson 2018-05-22 16:28:33 -07:00 • committed by Stafford Horne
parent c28fa81f91
commit 455d45d22c
6 changed files with 46 additions and 49 deletions
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6
target/openrisc/cpu.h
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@ -301,6 +301,10 @@ typedef struct CPUOpenRISCState {
uint32_t dflag; /* In delay slot (boolean) */
#ifndef CONFIG_USER_ONLY
CPUOpenRISCTLBContext tlb;
#endif
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@ -310,8 +314,6 @@ typedef struct CPUOpenRISCState {
uint32_t cpucfgr; /* CPU configure register */
#ifndef CONFIG_USER_ONLY
CPUOpenRISCTLBContext * tlb;
QEMUTimer *timer;
uint32_t ttmr; /* Timer tick mode register */
int is_counting;