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target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled
To implement PAN, we will want to swap, for short periods of time, to a different privileged mmu_idx. In addition, we cannot do this with flushing alone, because the AT* instructions have both PAN and PAN-less versions. Add the ARMMMUIdx*_PAN constants where necessary next to the corresponding ARMMMUIdx* constant. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
fee7aa46ed
commit
452ef8cb8c
6 changed files with 87 additions and 22 deletions
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@ -671,6 +671,7 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
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tlb_flush_by_mmuidx(cs,
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ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0 |
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ARMMMUIdxBit_Stage2);
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}
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@ -682,6 +683,7 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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tlb_flush_by_mmuidx_all_cpus_synced(cs,
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ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0 |
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ARMMMUIdxBit_Stage2);
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}
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@ -2700,6 +2702,7 @@ static int gt_phys_redir_timeridx(CPUARMState *env)
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switch (arm_mmu_idx(env)) {
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case ARMMMUIdx_E20_0:
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case ARMMMUIdx_E20_2:
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case ARMMMUIdx_E20_2_PAN:
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return GTIMER_HYP;
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default:
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return GTIMER_PHYS;
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@ -2711,6 +2714,7 @@ static int gt_virt_redir_timeridx(CPUARMState *env)
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switch (arm_mmu_idx(env)) {
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case ARMMMUIdx_E20_0:
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case ARMMMUIdx_E20_2:
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case ARMMMUIdx_E20_2_PAN:
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return GTIMER_HYPVIRT;
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default:
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return GTIMER_VIRT;
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@ -3337,7 +3341,9 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
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if (mmu_idx == ARMMMUIdx_E10_0 ||
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mmu_idx == ARMMMUIdx_E10_1 ||
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mmu_idx == ARMMMUIdx_E10_1_PAN) {
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format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
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} else {
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format64 |= arm_current_el(env) == 2;
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@ -3797,7 +3803,9 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
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(arm_hcr_el2_eff(env) & HCR_E2H)) {
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tlb_flush_by_mmuidx(env_cpu(env),
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ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0);
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ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0);
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}
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raw_write(env, ri, value);
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}
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@ -3815,6 +3823,7 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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if (raw_read(env, ri) != value) {
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tlb_flush_by_mmuidx(cs,
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ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0 |
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ARMMMUIdxBit_Stage2);
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raw_write(env, ri, value);
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@ -4175,12 +4184,18 @@ static int vae1_tlbmask(CPUARMState *env)
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{
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/* Since we exclude secure first, we may read HCR_EL2 directly. */
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
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return ARMMMUIdxBit_SE10_1 |
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ARMMMUIdxBit_SE10_1_PAN |
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ARMMMUIdxBit_SE10_0;
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} else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
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== (HCR_E2H | HCR_TGE)) {
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return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
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return ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else {
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return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
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return ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0;
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}
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}
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@ -4214,18 +4229,28 @@ static int alle1_tlbmask(CPUARMState *env)
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* stage 1 translations.
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*/
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
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return ARMMMUIdxBit_SE10_1 |
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ARMMMUIdxBit_SE10_1_PAN |
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ARMMMUIdxBit_SE10_0;
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} else if (arm_feature(env, ARM_FEATURE_EL2)) {
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return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2;
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return ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0 |
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ARMMMUIdxBit_Stage2;
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} else {
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return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
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return ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0;
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}
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}
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static int e2_tlbmask(CPUARMState *env)
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{
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/* TODO: ARMv8.4-SecEL2 */
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return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
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return ARMMMUIdxBit_E20_0 |
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ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E2;
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}
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static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -9206,6 +9231,7 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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switch (mmu_idx) {
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case ARMMMUIdx_E20_0:
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case ARMMMUIdx_E20_2:
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case ARMMMUIdx_E20_2_PAN:
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case ARMMMUIdx_Stage2:
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case ARMMMUIdx_E2:
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return 2;
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@ -9214,10 +9240,13 @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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case ARMMMUIdx_SE10_0:
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return arm_el_is_aa64(env, 3) ? 1 : 3;
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case ARMMMUIdx_SE10_1:
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case ARMMMUIdx_SE10_1_PAN:
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case ARMMMUIdx_Stage1_E0:
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case ARMMMUIdx_Stage1_E1:
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case ARMMMUIdx_Stage1_E1_PAN:
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case ARMMMUIdx_E10_0:
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case ARMMMUIdx_E10_1:
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case ARMMMUIdx_E10_1_PAN:
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case ARMMMUIdx_MPrivNegPri:
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case ARMMMUIdx_MUserNegPri:
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case ARMMMUIdx_MPriv:
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@ -9333,6 +9362,8 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
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return ARMMMUIdx_Stage1_E0;
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case ARMMMUIdx_E10_1:
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return ARMMMUIdx_Stage1_E1;
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case ARMMMUIdx_E10_1_PAN:
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return ARMMMUIdx_Stage1_E1_PAN;
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default:
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return mmu_idx;
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}
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@ -9379,6 +9410,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
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return false;
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case ARMMMUIdx_E10_0:
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case ARMMMUIdx_E10_1:
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case ARMMMUIdx_E10_1_PAN:
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g_assert_not_reached();
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}
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}
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@ -11271,7 +11303,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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{
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if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
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if (mmu_idx == ARMMMUIdx_E10_0 ||
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mmu_idx == ARMMMUIdx_E10_1 ||
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mmu_idx == ARMMMUIdx_E10_1_PAN) {
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/* Call ourselves recursively to do the stage 1 and then stage 2
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* translations.
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*/
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@ -11798,10 +11832,13 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
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case ARMMMUIdx_SE10_0:
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return 0;
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case ARMMMUIdx_E10_1:
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case ARMMMUIdx_E10_1_PAN:
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case ARMMMUIdx_SE10_1:
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case ARMMMUIdx_SE10_1_PAN:
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return 1;
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case ARMMMUIdx_E2:
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case ARMMMUIdx_E20_2:
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case ARMMMUIdx_E20_2_PAN:
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return 2;
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case ARMMMUIdx_SE3:
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return 3;
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@ -12018,11 +12055,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
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/* TODO: ARMv8.2-UAO */
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switch (mmu_idx) {
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case ARMMMUIdx_E10_1:
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case ARMMMUIdx_E10_1_PAN:
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case ARMMMUIdx_SE10_1:
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case ARMMMUIdx_SE10_1_PAN:
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/* TODO: ARMv8.3-NV */
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flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
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break;
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case ARMMMUIdx_E20_2:
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case ARMMMUIdx_E20_2_PAN:
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/* TODO: ARMv8.4-SecEL2 */
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/*
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* Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is
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