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linux-headers: Update to Linux 6.13-rc1
This linux headers update includes required changes for the gen17 CPU model. Signed-off-by: Hendrik Brueckner <brueckner@linux.ibm.com> Suggested-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241206122751.189721-7-brueckner@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Hendrik Brueckner
Thomas Huth
parent
eba6f49128
commit
44fe383c27
33 changed files with 506 additions and 23 deletions
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@ -1515,6 +1515,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
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* 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
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*/
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#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
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#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22
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#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
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#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
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#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
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@ -2526,6 +2526,11 @@ struct ethtool_link_settings {
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uint8_t master_slave_state;
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uint8_t rate_matching;
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uint32_t reserved[7];
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/* Linux builds with -Wflex-array-member-not-at-end but does
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* not use the "link_mode_masks" member. Leave it defined for
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* userspace for now, and when userspace wants to start using
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* -Wfamnae, we'll need a new solution.
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*/
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uint32_t link_mode_masks[];
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/* layout of link_mode_masks fields:
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* uint32_t map_supported[link_mode_masks_nwords];
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@ -340,7 +340,8 @@
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#define PCI_MSIX_ENTRY_UPPER_ADDR 0x4 /* Message Upper Address */
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#define PCI_MSIX_ENTRY_DATA 0x8 /* Message Data */
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 0xc /* Vector Control */
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* Mask Bit */
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#define PCI_MSIX_ENTRY_CTRL_ST 0xffff0000 /* Steering Tag */
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/* CompactPCI Hotswap Register */
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@ -659,6 +660,7 @@
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */
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#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCAP2_TPH_COMP_MASK 0x00003000 /* TPH completer support */
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
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@ -678,6 +680,7 @@
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#define PCI_EXP_DEVSTA2 0x2a /* Device Status 2 */
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#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c /* end of v2 EPs w/o link */
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#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities 2 */
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#define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
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#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
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#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
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@ -1023,15 +1026,34 @@
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#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
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#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */
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/* TPH Completer Support */
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#define PCI_EXP_DEVCAP2_TPH_COMP_NONE 0x0 /* None */
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#define PCI_EXP_DEVCAP2_TPH_COMP_TPH_ONLY 0x1 /* TPH only */
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#define PCI_EXP_DEVCAP2_TPH_COMP_EXT_TPH 0x3 /* TPH and Extended TPH */
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/* TPH Requester */
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#define PCI_TPH_CAP 4 /* capability register */
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#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
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#define PCI_TPH_LOC_NONE 0x000 /* no location */
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#define PCI_TPH_LOC_CAP 0x200 /* in capability */
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#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
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#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST table mask */
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#define PCI_TPH_CAP_ST_SHIFT 16 /* ST table shift */
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#define PCI_TPH_BASE_SIZEOF 0xc /* size with no ST table */
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#define PCI_TPH_CAP_ST_NS 0x00000001 /* No ST Mode Supported */
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#define PCI_TPH_CAP_ST_IV 0x00000002 /* Interrupt Vector Mode Supported */
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#define PCI_TPH_CAP_ST_DS 0x00000004 /* Device Specific Mode Supported */
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#define PCI_TPH_CAP_EXT_TPH 0x00000100 /* Ext TPH Requester Supported */
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#define PCI_TPH_CAP_LOC_MASK 0x00000600 /* ST Table Location */
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#define PCI_TPH_LOC_NONE 0x00000000 /* Not present */
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#define PCI_TPH_LOC_CAP 0x00000200 /* In capability */
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#define PCI_TPH_LOC_MSIX 0x00000400 /* In MSI-X */
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#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* ST Table Size */
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#define PCI_TPH_CAP_ST_SHIFT 16 /* ST Table Size shift */
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#define PCI_TPH_BASE_SIZEOF 0xc /* Size with no ST table */
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#define PCI_TPH_CTRL 8 /* control register */
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#define PCI_TPH_CTRL_MODE_SEL_MASK 0x00000007 /* ST Mode Select */
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#define PCI_TPH_ST_NS_MODE 0x0 /* No ST Mode */
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#define PCI_TPH_ST_IV_MODE 0x1 /* Interrupt Vector Mode */
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#define PCI_TPH_ST_DS_MODE 0x2 /* Device Specific Mode */
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#define PCI_TPH_CTRL_REQ_EN_MASK 0x00000300 /* TPH Requester Enable */
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#define PCI_TPH_REQ_DISABLE 0x0 /* No TPH requests allowed */
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#define PCI_TPH_REQ_TPH_ONLY 0x1 /* TPH only requests allowed */
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#define PCI_TPH_REQ_EXT_TPH 0x3 /* Extended TPH requests allowed */
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/* Downstream Port Containment */
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#define PCI_EXP_DPC_CAP 0x04 /* DPC Capability */
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@ -329,6 +329,7 @@ struct virtio_crypto_op_header {
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VIRTIO_CRYPTO_OPCODE(VIRTIO_CRYPTO_SERVICE_AKCIPHER, 0x00)
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#define VIRTIO_CRYPTO_AKCIPHER_DECRYPT \
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VIRTIO_CRYPTO_OPCODE(VIRTIO_CRYPTO_SERVICE_AKCIPHER, 0x01)
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/* akcipher sign/verify opcodes are deprecated */
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#define VIRTIO_CRYPTO_AKCIPHER_SIGN \
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VIRTIO_CRYPTO_OPCODE(VIRTIO_CRYPTO_SERVICE_AKCIPHER, 0x02)
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#define VIRTIO_CRYPTO_AKCIPHER_VERIFY \
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@ -40,6 +40,7 @@
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#define _LINUX_VIRTIO_PCI_H
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#include "standard-headers/linux/types.h"
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#include "standard-headers/linux/kernel.h"
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#ifndef VIRTIO_PCI_NO_LEGACY
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@ -240,6 +241,17 @@ struct virtio_pci_cfg_cap {
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#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ 0x5
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#define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO 0x6
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/* Device parts access commands. */
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#define VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY 0x7
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#define VIRTIO_ADMIN_CMD_DEVICE_CAP_GET 0x8
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#define VIRTIO_ADMIN_CMD_DRIVER_CAP_SET 0x9
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#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_CREATE 0xa
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#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_DESTROY 0xd
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_GET 0xe
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET 0xf
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_SET 0x10
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#define VIRTIO_ADMIN_CMD_DEV_MODE_SET 0x11
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struct virtio_admin_cmd_hdr {
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uint16_t opcode;
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/*
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@ -286,4 +298,123 @@ struct virtio_admin_cmd_notify_info_result {
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struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
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};
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#define VIRTIO_DEV_PARTS_CAP 0x0000
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struct virtio_dev_parts_cap {
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uint8_t get_parts_resource_objects_limit;
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uint8_t set_parts_resource_objects_limit;
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};
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#define MAX_CAP_ID __KERNEL_DIV_ROUND_UP(VIRTIO_DEV_PARTS_CAP + 1, 64)
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struct virtio_admin_cmd_query_cap_id_result {
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uint64_t supported_caps[MAX_CAP_ID];
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};
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struct virtio_admin_cmd_cap_get_data {
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uint16_t id;
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uint8_t reserved[6];
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};
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struct virtio_admin_cmd_cap_set_data {
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uint16_t id;
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uint8_t reserved[6];
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uint8_t cap_specific_data[];
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};
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struct virtio_admin_cmd_resource_obj_cmd_hdr {
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uint16_t type;
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uint8_t reserved[2];
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uint32_t id; /* Indicates unique resource object id per resource object type */
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};
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struct virtio_admin_cmd_resource_obj_create_data {
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struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
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uint64_t flags;
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uint8_t resource_obj_specific_data[];
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};
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#define VIRTIO_RESOURCE_OBJ_DEV_PARTS 0
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#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_GET 0
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#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_SET 1
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struct virtio_resource_obj_dev_parts {
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uint8_t type;
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uint8_t reserved[7];
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};
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_SIZE 0
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_COUNT 1
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_LIST 2
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struct virtio_admin_cmd_dev_parts_metadata_data {
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struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
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uint8_t type;
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uint8_t reserved[7];
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};
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#define VIRTIO_DEV_PART_F_OPTIONAL 0
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struct virtio_dev_part_hdr {
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uint16_t part_type;
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uint8_t flags;
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uint8_t reserved;
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union {
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struct {
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uint32_t offset;
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uint32_t reserved;
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} pci_common_cfg;
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struct {
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uint16_t index;
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uint8_t reserved[6];
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} vq_index;
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} selector;
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uint32_t length;
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};
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struct virtio_dev_part {
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struct virtio_dev_part_hdr hdr;
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uint8_t value[];
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};
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struct virtio_admin_cmd_dev_parts_metadata_result {
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union {
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struct {
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uint32_t size;
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uint32_t reserved;
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} parts_size;
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struct {
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uint32_t count;
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uint32_t reserved;
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} hdr_list_count;
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struct {
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uint32_t count;
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uint32_t reserved;
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struct virtio_dev_part_hdr hdrs[];
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} hdr_list;
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};
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};
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_SELECTED 0
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#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_ALL 1
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struct virtio_admin_cmd_dev_parts_get_data {
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struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
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uint8_t type;
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uint8_t reserved[7];
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struct virtio_dev_part_hdr hdr_list[];
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};
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struct virtio_admin_cmd_dev_parts_set_data {
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struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
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struct virtio_dev_part parts[];
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};
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#define VIRTIO_ADMIN_CMD_DEV_MODE_F_STOPPED 0
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struct virtio_admin_cmd_dev_mode_set_data {
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uint8_t flags;
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};
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#endif
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@ -473,6 +473,12 @@ enum {
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*/
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#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0)
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/*
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* Shutdown caused by a PSCI v1.3 SYSTEM_OFF2 call.
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* Valid only when the system event has a type of KVM_SYSTEM_EVENT_SHUTDOWN.
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*/
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#define KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 (1ULL << 0)
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/* run->fail_entry.hardware_entry_failure_reason codes. */
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#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0)
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@ -319,6 +319,10 @@
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#define __NR_lsm_set_self_attr 460
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#define __NR_lsm_list_modules 461
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#define __NR_mseal 462
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#define __NR_setxattrat 463
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#define __NR_getxattrat 464
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#define __NR_listxattrat 465
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#define __NR_removexattrat 466
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#endif /* _ASM_UNISTD_64_H */
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@ -79,6 +79,9 @@
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#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
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#define MADV_GUARD_INSTALL 102 /* fatal signal on access to range */
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#define MADV_GUARD_REMOVE 103 /* unguard range */
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/* compatibility flags */
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#define MAP_FILE 0
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@ -19,4 +19,8 @@
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#define MCL_FUTURE 2 /* lock all future mappings */
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#define MCL_ONFAULT 4 /* lock all pages that are faulted in */
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#define SHADOW_STACK_SET_TOKEN (1ULL << 0) /* Set up a restore token in the shadow stack */
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#define SHADOW_STACK_SET_MARKER (1ULL << 1) /* Set up a top of stack marker in the shadow stack */
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#endif /* __ASM_GENERIC_MMAN_H */
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@ -841,8 +841,17 @@ __SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules)
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#define __NR_mseal 462
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__SYSCALL(__NR_mseal, sys_mseal)
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#define __NR_setxattrat 463
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__SYSCALL(__NR_setxattrat, sys_setxattrat)
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#define __NR_getxattrat 464
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__SYSCALL(__NR_getxattrat, sys_getxattrat)
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#define __NR_listxattrat 465
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__SYSCALL(__NR_listxattrat, sys_listxattrat)
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#define __NR_removexattrat 466
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__SYSCALL(__NR_removexattrat, sys_removexattrat)
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#undef __NR_syscalls
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#define __NR_syscalls 463
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#define __NR_syscalls 467
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/*
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* 32 bit systems traditionally used different
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@ -8,6 +8,8 @@
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#include <linux/types.h>
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#define __KVM_HAVE_IRQ_LINE
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/*
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* KVM LoongArch specific structures and definitions.
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*
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@ -132,4 +134,22 @@ struct kvm_iocsr_entry {
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#define KVM_IRQCHIP_NUM_PINS 64
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#define KVM_MAX_CORES 256
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#define KVM_DEV_LOONGARCH_IPI_GRP_REGS 0x40000001
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#define KVM_DEV_LOONGARCH_EXTIOI_GRP_REGS 0x40000002
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#define KVM_DEV_LOONGARCH_EXTIOI_GRP_SW_STATUS 0x40000003
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#define KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_NUM_CPU 0x0
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#define KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_FEATURE 0x1
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#define KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_STATE 0x2
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#define KVM_DEV_LOONGARCH_EXTIOI_GRP_CTRL 0x40000004
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#define KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_NUM_CPU 0x0
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#define KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_FEATURE 0x1
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#define KVM_DEV_LOONGARCH_EXTIOI_CTRL_LOAD_FINISHED 0x3
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#define KVM_DEV_LOONGARCH_PCH_PIC_GRP_REGS 0x40000005
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#define KVM_DEV_LOONGARCH_PCH_PIC_GRP_CTRL 0x40000006
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#define KVM_DEV_LOONGARCH_PCH_PIC_CTRL_INIT 0
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#endif /* __UAPI_ASM_LOONGARCH_KVM_H */
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@ -315,6 +315,10 @@
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#define __NR_lsm_set_self_attr 460
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#define __NR_lsm_list_modules 461
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#define __NR_mseal 462
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#define __NR_setxattrat 463
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#define __NR_getxattrat 464
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#define __NR_listxattrat 465
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#define __NR_removexattrat 466
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#endif /* _ASM_UNISTD_64_H */
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@ -105,6 +105,9 @@
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#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
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#define MADV_GUARD_INSTALL 102 /* fatal signal on access to range */
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#define MADV_GUARD_REMOVE 103 /* unguard range */
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/* compatibility flags */
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#define MAP_FILE 0
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@ -391,5 +391,9 @@
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#define __NR_lsm_set_self_attr (__NR_Linux + 460)
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#define __NR_lsm_list_modules (__NR_Linux + 461)
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#define __NR_mseal (__NR_Linux + 462)
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#define __NR_setxattrat (__NR_Linux + 463)
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#define __NR_getxattrat (__NR_Linux + 464)
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#define __NR_listxattrat (__NR_Linux + 465)
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#define __NR_removexattrat (__NR_Linux + 466)
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#endif /* _ASM_UNISTD_N32_H */
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|
|
|||
|
|
@ -367,5 +367,9 @@
|
|||
#define __NR_lsm_set_self_attr (__NR_Linux + 460)
|
||||
#define __NR_lsm_list_modules (__NR_Linux + 461)
|
||||
#define __NR_mseal (__NR_Linux + 462)
|
||||
#define __NR_setxattrat (__NR_Linux + 463)
|
||||
#define __NR_getxattrat (__NR_Linux + 464)
|
||||
#define __NR_listxattrat (__NR_Linux + 465)
|
||||
#define __NR_removexattrat (__NR_Linux + 466)
|
||||
|
||||
#endif /* _ASM_UNISTD_N64_H */
|
||||
|
|
|
|||
|
|
@ -437,5 +437,9 @@
|
|||
#define __NR_lsm_set_self_attr (__NR_Linux + 460)
|
||||
#define __NR_lsm_list_modules (__NR_Linux + 461)
|
||||
#define __NR_mseal (__NR_Linux + 462)
|
||||
#define __NR_setxattrat (__NR_Linux + 463)
|
||||
#define __NR_getxattrat (__NR_Linux + 464)
|
||||
#define __NR_listxattrat (__NR_Linux + 465)
|
||||
#define __NR_removexattrat (__NR_Linux + 466)
|
||||
|
||||
#endif /* _ASM_UNISTD_O32_H */
|
||||
|
|
|
|||
|
|
@ -444,6 +444,10 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
|
||||
#endif /* _ASM_UNISTD_32_H */
|
||||
|
|
|
|||
|
|
@ -416,6 +416,10 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
|
||||
#endif /* _ASM_UNISTD_64_H */
|
||||
|
|
|
|||
|
|
@ -175,6 +175,10 @@ enum KVM_RISCV_ISA_EXT_ID {
|
|||
KVM_RISCV_ISA_EXT_ZCF,
|
||||
KVM_RISCV_ISA_EXT_ZCMOP,
|
||||
KVM_RISCV_ISA_EXT_ZAWRS,
|
||||
KVM_RISCV_ISA_EXT_SMNPM,
|
||||
KVM_RISCV_ISA_EXT_SSNPM,
|
||||
KVM_RISCV_ISA_EXT_SVADE,
|
||||
KVM_RISCV_ISA_EXT_SVADU,
|
||||
KVM_RISCV_ISA_EXT_MAX,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -310,6 +310,10 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
|
||||
#endif /* _ASM_UNISTD_32_H */
|
||||
|
|
|
|||
|
|
@ -320,6 +320,10 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
|
||||
#endif /* _ASM_UNISTD_64_H */
|
||||
|
|
|
|||
|
|
@ -469,7 +469,8 @@ struct kvm_s390_vm_cpu_subfunc {
|
|||
__u8 kdsa[16]; /* with MSA9 */
|
||||
__u8 sortl[32]; /* with STFLE.150 */
|
||||
__u8 dfltcc[32]; /* with STFLE.151 */
|
||||
__u8 reserved[1728];
|
||||
__u8 pfcr[16]; /* with STFLE.201 */
|
||||
__u8 reserved[1712];
|
||||
};
|
||||
|
||||
#define KVM_S390_VM_CPU_PROCESSOR_UV_FEAT_GUEST 6
|
||||
|
|
|
|||
|
|
@ -435,5 +435,9 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
#endif /* _ASM_S390_UNISTD_32_H */
|
||||
|
|
|
|||
|
|
@ -383,5 +383,9 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
#endif /* _ASM_S390_UNISTD_64_H */
|
||||
|
|
|
|||
|
|
@ -438,6 +438,7 @@ struct kvm_sync_regs {
|
|||
#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5)
|
||||
#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6)
|
||||
#define KVM_X86_QUIRK_SLOT_ZAP_ALL (1 << 7)
|
||||
#define KVM_X86_QUIRK_STUFF_FEATURE_MSRS (1 << 8)
|
||||
|
||||
#define KVM_STATE_NESTED_FORMAT_VMX 0
|
||||
#define KVM_STATE_NESTED_FORMAT_SVM 1
|
||||
|
|
|
|||
|
|
@ -5,9 +5,6 @@
|
|||
#define MAP_32BIT 0x40 /* only give out 32bit addresses */
|
||||
#define MAP_ABOVE4G 0x80 /* only map above 4GB */
|
||||
|
||||
/* Flags for map_shadow_stack(2) */
|
||||
#define SHADOW_STACK_SET_TOKEN (1ULL << 0) /* Set up a restore token in the shadow stack */
|
||||
|
||||
#include <asm-generic/mman.h>
|
||||
|
||||
#endif /* _ASM_X86_MMAN_H */
|
||||
|
|
|
|||
|
|
@ -453,6 +453,10 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
|
||||
#endif /* _ASM_UNISTD_32_H */
|
||||
|
|
|
|||
|
|
@ -376,6 +376,10 @@
|
|||
#define __NR_lsm_set_self_attr 460
|
||||
#define __NR_lsm_list_modules 461
|
||||
#define __NR_mseal 462
|
||||
#define __NR_setxattrat 463
|
||||
#define __NR_getxattrat 464
|
||||
#define __NR_listxattrat 465
|
||||
#define __NR_removexattrat 466
|
||||
|
||||
|
||||
#endif /* _ASM_UNISTD_64_H */
|
||||
|
|
|
|||
|
|
@ -329,6 +329,10 @@
|
|||
#define __NR_lsm_set_self_attr (__X32_SYSCALL_BIT + 460)
|
||||
#define __NR_lsm_list_modules (__X32_SYSCALL_BIT + 461)
|
||||
#define __NR_mseal (__X32_SYSCALL_BIT + 462)
|
||||
#define __NR_setxattrat (__X32_SYSCALL_BIT + 463)
|
||||
#define __NR_getxattrat (__X32_SYSCALL_BIT + 464)
|
||||
#define __NR_listxattrat (__X32_SYSCALL_BIT + 465)
|
||||
#define __NR_removexattrat (__X32_SYSCALL_BIT + 466)
|
||||
#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
|
||||
#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
|
||||
#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
|
||||
|
|
|
|||
|
|
@ -51,6 +51,10 @@ enum {
|
|||
IOMMUFD_CMD_HWPT_GET_DIRTY_BITMAP = 0x8c,
|
||||
IOMMUFD_CMD_HWPT_INVALIDATE = 0x8d,
|
||||
IOMMUFD_CMD_FAULT_QUEUE_ALLOC = 0x8e,
|
||||
IOMMUFD_CMD_IOAS_MAP_FILE = 0x8f,
|
||||
IOMMUFD_CMD_VIOMMU_ALLOC = 0x90,
|
||||
IOMMUFD_CMD_VDEVICE_ALLOC = 0x91,
|
||||
IOMMUFD_CMD_IOAS_CHANGE_PROCESS = 0x92,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -213,6 +217,30 @@ struct iommu_ioas_map {
|
|||
};
|
||||
#define IOMMU_IOAS_MAP _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP)
|
||||
|
||||
/**
|
||||
* struct iommu_ioas_map_file - ioctl(IOMMU_IOAS_MAP_FILE)
|
||||
* @size: sizeof(struct iommu_ioas_map_file)
|
||||
* @flags: same as for iommu_ioas_map
|
||||
* @ioas_id: same as for iommu_ioas_map
|
||||
* @fd: the memfd to map
|
||||
* @start: byte offset from start of file to map from
|
||||
* @length: same as for iommu_ioas_map
|
||||
* @iova: same as for iommu_ioas_map
|
||||
*
|
||||
* Set an IOVA mapping from a memfd file. All other arguments and semantics
|
||||
* match those of IOMMU_IOAS_MAP.
|
||||
*/
|
||||
struct iommu_ioas_map_file {
|
||||
__u32 size;
|
||||
__u32 flags;
|
||||
__u32 ioas_id;
|
||||
__s32 fd;
|
||||
__aligned_u64 start;
|
||||
__aligned_u64 length;
|
||||
__aligned_u64 iova;
|
||||
};
|
||||
#define IOMMU_IOAS_MAP_FILE _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_MAP_FILE)
|
||||
|
||||
/**
|
||||
* struct iommu_ioas_copy - ioctl(IOMMU_IOAS_COPY)
|
||||
* @size: sizeof(struct iommu_ioas_copy)
|
||||
|
|
@ -359,11 +387,19 @@ struct iommu_vfio_ioas {
|
|||
* enforced on device attachment
|
||||
* @IOMMU_HWPT_FAULT_ID_VALID: The fault_id field of hwpt allocation data is
|
||||
* valid.
|
||||
* @IOMMU_HWPT_ALLOC_PASID: Requests a domain that can be used with PASID. The
|
||||
* domain can be attached to any PASID on the device.
|
||||
* Any domain attached to the non-PASID part of the
|
||||
* device must also be flaged, otherwise attaching a
|
||||
* PASID will blocked.
|
||||
* If IOMMU does not support PASID it will return
|
||||
* error (-EOPNOTSUPP).
|
||||
*/
|
||||
enum iommufd_hwpt_alloc_flags {
|
||||
IOMMU_HWPT_ALLOC_NEST_PARENT = 1 << 0,
|
||||
IOMMU_HWPT_ALLOC_DIRTY_TRACKING = 1 << 1,
|
||||
IOMMU_HWPT_FAULT_ID_VALID = 1 << 2,
|
||||
IOMMU_HWPT_ALLOC_PASID = 1 << 3,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -394,14 +430,36 @@ struct iommu_hwpt_vtd_s1 {
|
|||
__u32 __reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 nested STE
|
||||
* (IOMMU_HWPT_DATA_ARM_SMMUV3)
|
||||
*
|
||||
* @ste: The first two double words of the user space Stream Table Entry for
|
||||
* the translation. Must be little-endian.
|
||||
* Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec)
|
||||
* - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax
|
||||
* - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD
|
||||
*
|
||||
* -EIO will be returned if @ste is not legal or contains any non-allowed field.
|
||||
* Cfg can be used to select a S1, Bypass or Abort configuration. A Bypass
|
||||
* nested domain will translate the same as the nesting parent. The S1 will
|
||||
* install a Context Descriptor Table pointing at userspace memory translated
|
||||
* by the nesting parent.
|
||||
*/
|
||||
struct iommu_hwpt_arm_smmuv3 {
|
||||
__aligned_le64 ste[2];
|
||||
};
|
||||
|
||||
/**
|
||||
* enum iommu_hwpt_data_type - IOMMU HWPT Data Type
|
||||
* @IOMMU_HWPT_DATA_NONE: no data
|
||||
* @IOMMU_HWPT_DATA_VTD_S1: Intel VT-d stage-1 page table
|
||||
* @IOMMU_HWPT_DATA_ARM_SMMUV3: ARM SMMUv3 Context Descriptor Table
|
||||
*/
|
||||
enum iommu_hwpt_data_type {
|
||||
IOMMU_HWPT_DATA_NONE = 0,
|
||||
IOMMU_HWPT_DATA_VTD_S1 = 1,
|
||||
IOMMU_HWPT_DATA_ARM_SMMUV3 = 2,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -409,7 +467,7 @@ enum iommu_hwpt_data_type {
|
|||
* @size: sizeof(struct iommu_hwpt_alloc)
|
||||
* @flags: Combination of enum iommufd_hwpt_alloc_flags
|
||||
* @dev_id: The device to allocate this HWPT for
|
||||
* @pt_id: The IOAS or HWPT to connect this HWPT to
|
||||
* @pt_id: The IOAS or HWPT or vIOMMU to connect this HWPT to
|
||||
* @out_hwpt_id: The ID of the new HWPT
|
||||
* @__reserved: Must be 0
|
||||
* @data_type: One of enum iommu_hwpt_data_type
|
||||
|
|
@ -428,11 +486,13 @@ enum iommu_hwpt_data_type {
|
|||
* IOMMU_HWPT_DATA_NONE. The HWPT can be allocated as a parent HWPT for a
|
||||
* nesting configuration by passing IOMMU_HWPT_ALLOC_NEST_PARENT via @flags.
|
||||
*
|
||||
* A user-managed nested HWPT will be created from a given parent HWPT via
|
||||
* @pt_id, in which the parent HWPT must be allocated previously via the
|
||||
* same ioctl from a given IOAS (@pt_id). In this case, the @data_type
|
||||
* must be set to a pre-defined type corresponding to an I/O page table
|
||||
* type supported by the underlying IOMMU hardware.
|
||||
* A user-managed nested HWPT will be created from a given vIOMMU (wrapping a
|
||||
* parent HWPT) or a parent HWPT via @pt_id, in which the parent HWPT must be
|
||||
* allocated previously via the same ioctl from a given IOAS (@pt_id). In this
|
||||
* case, the @data_type must be set to a pre-defined type corresponding to an
|
||||
* I/O page table type supported by the underlying IOMMU hardware. The device
|
||||
* via @dev_id and the vIOMMU via @pt_id must be associated to the same IOMMU
|
||||
* instance.
|
||||
*
|
||||
* If the @data_type is set to IOMMU_HWPT_DATA_NONE, @data_len and
|
||||
* @data_uptr should be zero. Otherwise, both @data_len and @data_uptr
|
||||
|
|
@ -484,15 +544,50 @@ struct iommu_hw_info_vtd {
|
|||
__aligned_u64 ecap_reg;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information
|
||||
* (IOMMU_HW_INFO_TYPE_ARM_SMMUV3)
|
||||
*
|
||||
* @flags: Must be set to 0
|
||||
* @__reserved: Must be 0
|
||||
* @idr: Implemented features for ARM SMMU Non-secure programming interface
|
||||
* @iidr: Information about the implementation and implementer of ARM SMMU,
|
||||
* and architecture version supported
|
||||
* @aidr: ARM SMMU architecture version
|
||||
*
|
||||
* For the details of @idr, @iidr and @aidr, please refer to the chapters
|
||||
* from 6.3.1 to 6.3.6 in the SMMUv3 Spec.
|
||||
*
|
||||
* User space should read the underlying ARM SMMUv3 hardware information for
|
||||
* the list of supported features.
|
||||
*
|
||||
* Note that these values reflect the raw HW capability, without any insight if
|
||||
* any required kernel driver support is present. Bits may be set indicating the
|
||||
* HW has functionality that is lacking kernel software support, such as BTM. If
|
||||
* a VMM is using this information to construct emulated copies of these
|
||||
* registers it should only forward bits that it knows it can support.
|
||||
*
|
||||
* In future, presence of required kernel support will be indicated in flags.
|
||||
*/
|
||||
struct iommu_hw_info_arm_smmuv3 {
|
||||
__u32 flags;
|
||||
__u32 __reserved;
|
||||
__u32 idr[6];
|
||||
__u32 iidr;
|
||||
__u32 aidr;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum iommu_hw_info_type - IOMMU Hardware Info Types
|
||||
* @IOMMU_HW_INFO_TYPE_NONE: Used by the drivers that do not report hardware
|
||||
* info
|
||||
* @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type
|
||||
* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type
|
||||
*/
|
||||
enum iommu_hw_info_type {
|
||||
IOMMU_HW_INFO_TYPE_NONE = 0,
|
||||
IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,
|
||||
IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -627,9 +722,11 @@ struct iommu_hwpt_get_dirty_bitmap {
|
|||
* enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
|
||||
* Data Type
|
||||
* @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
|
||||
* @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3
|
||||
*/
|
||||
enum iommu_hwpt_invalidate_data_type {
|
||||
IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0,
|
||||
IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -668,10 +765,32 @@ struct iommu_hwpt_vtd_s1_invalidate {
|
|||
__u32 __reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cahce invalidation
|
||||
* (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3)
|
||||
* @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ.
|
||||
* Must be little-endian.
|
||||
*
|
||||
* Supported command list only when passing in a vIOMMU via @hwpt_id:
|
||||
* CMDQ_OP_TLBI_NSNH_ALL
|
||||
* CMDQ_OP_TLBI_NH_VA
|
||||
* CMDQ_OP_TLBI_NH_VAA
|
||||
* CMDQ_OP_TLBI_NH_ALL
|
||||
* CMDQ_OP_TLBI_NH_ASID
|
||||
* CMDQ_OP_ATC_INV
|
||||
* CMDQ_OP_CFGI_CD
|
||||
* CMDQ_OP_CFGI_CD_ALL
|
||||
*
|
||||
* -EIO will be returned if the command is not supported.
|
||||
*/
|
||||
struct iommu_viommu_arm_smmuv3_invalidate {
|
||||
__aligned_le64 cmd[2];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
|
||||
* @size: sizeof(struct iommu_hwpt_invalidate)
|
||||
* @hwpt_id: ID of a nested HWPT for cache invalidation
|
||||
* @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation
|
||||
* @data_uptr: User pointer to an array of driver-specific cache invalidation
|
||||
* data.
|
||||
* @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data
|
||||
|
|
@ -682,8 +801,11 @@ struct iommu_hwpt_vtd_s1_invalidate {
|
|||
* Output the number of requests successfully handled by kernel.
|
||||
* @__reserved: Must be 0.
|
||||
*
|
||||
* Invalidate the iommu cache for user-managed page table. Modifications on a
|
||||
* user-managed page table should be followed by this operation to sync cache.
|
||||
* Invalidate iommu cache for user-managed page table or vIOMMU. Modifications
|
||||
* on a user-managed page table should be followed by this operation, if a HWPT
|
||||
* is passed in via @hwpt_id. Other caches, such as device cache or descriptor
|
||||
* cache can be flushed if a vIOMMU is passed in via the @hwpt_id field.
|
||||
*
|
||||
* Each ioctl can support one or more cache invalidation requests in the array
|
||||
* that has a total size of @entry_len * @entry_num.
|
||||
*
|
||||
|
|
@ -797,4 +919,88 @@ struct iommu_fault_alloc {
|
|||
__u32 out_fault_fd;
|
||||
};
|
||||
#define IOMMU_FAULT_QUEUE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_FAULT_QUEUE_ALLOC)
|
||||
|
||||
/**
|
||||
* enum iommu_viommu_type - Virtual IOMMU Type
|
||||
* @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use
|
||||
* @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type
|
||||
*/
|
||||
enum iommu_viommu_type {
|
||||
IOMMU_VIOMMU_TYPE_DEFAULT = 0,
|
||||
IOMMU_VIOMMU_TYPE_ARM_SMMUV3 = 1,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC)
|
||||
* @size: sizeof(struct iommu_viommu_alloc)
|
||||
* @flags: Must be 0
|
||||
* @type: Type of the virtual IOMMU. Must be defined in enum iommu_viommu_type
|
||||
* @dev_id: The device's physical IOMMU will be used to back the virtual IOMMU
|
||||
* @hwpt_id: ID of a nesting parent HWPT to associate to
|
||||
* @out_viommu_id: Output virtual IOMMU ID for the allocated object
|
||||
*
|
||||
* Allocate a virtual IOMMU object, representing the underlying physical IOMMU's
|
||||
* virtualization support that is a security-isolated slice of the real IOMMU HW
|
||||
* that is unique to a specific VM. Operations global to the IOMMU are connected
|
||||
* to the vIOMMU, such as:
|
||||
* - Security namespace for guest owned ID, e.g. guest-controlled cache tags
|
||||
* - Non-device-affiliated event reporting, e.g. invalidation queue errors
|
||||
* - Access to a sharable nesting parent pagetable across physical IOMMUs
|
||||
* - Virtualization of various platforms IDs, e.g. RIDs and others
|
||||
* - Delivery of paravirtualized invalidation
|
||||
* - Direct assigned invalidation queues
|
||||
* - Direct assigned interrupts
|
||||
*/
|
||||
struct iommu_viommu_alloc {
|
||||
__u32 size;
|
||||
__u32 flags;
|
||||
__u32 type;
|
||||
__u32 dev_id;
|
||||
__u32 hwpt_id;
|
||||
__u32 out_viommu_id;
|
||||
};
|
||||
#define IOMMU_VIOMMU_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VIOMMU_ALLOC)
|
||||
|
||||
/**
|
||||
* struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC)
|
||||
* @size: sizeof(struct iommu_vdevice_alloc)
|
||||
* @viommu_id: vIOMMU ID to associate with the virtual device
|
||||
* @dev_id: The physical device to allocate a virtual instance on the vIOMMU
|
||||
* @out_vdevice_id: Object handle for the vDevice. Pass to IOMMU_DESTORY
|
||||
* @virt_id: Virtual device ID per vIOMMU, e.g. vSID of ARM SMMUv3, vDeviceID
|
||||
* of AMD IOMMU, and vRID of a nested Intel VT-d to a Context Table
|
||||
*
|
||||
* Allocate a virtual device instance (for a physical device) against a vIOMMU.
|
||||
* This instance holds the device's information (related to its vIOMMU) in a VM.
|
||||
*/
|
||||
struct iommu_vdevice_alloc {
|
||||
__u32 size;
|
||||
__u32 viommu_id;
|
||||
__u32 dev_id;
|
||||
__u32 out_vdevice_id;
|
||||
__aligned_u64 virt_id;
|
||||
};
|
||||
#define IOMMU_VDEVICE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VDEVICE_ALLOC)
|
||||
|
||||
/**
|
||||
* struct iommu_ioas_change_process - ioctl(VFIO_IOAS_CHANGE_PROCESS)
|
||||
* @size: sizeof(struct iommu_ioas_change_process)
|
||||
* @__reserved: Must be 0
|
||||
*
|
||||
* This transfers pinned memory counts for every memory map in every IOAS
|
||||
* in the context to the current process. This only supports maps created
|
||||
* with IOMMU_IOAS_MAP_FILE, and returns EINVAL if other maps are present.
|
||||
* If the ioctl returns a failure status, then nothing is changed.
|
||||
*
|
||||
* This API is useful for transferring operation of a device from one process
|
||||
* to another, such as during userland live update.
|
||||
*/
|
||||
struct iommu_ioas_change_process {
|
||||
__u32 size;
|
||||
__u32 __reserved;
|
||||
};
|
||||
|
||||
#define IOMMU_IOAS_CHANGE_PROCESS \
|
||||
_IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_CHANGE_PROCESS)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1150,7 +1150,15 @@ enum kvm_device_type {
|
|||
#define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME
|
||||
KVM_DEV_TYPE_RISCV_AIA,
|
||||
#define KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_RISCV_AIA
|
||||
KVM_DEV_TYPE_LOONGARCH_IPI,
|
||||
#define KVM_DEV_TYPE_LOONGARCH_IPI KVM_DEV_TYPE_LOONGARCH_IPI
|
||||
KVM_DEV_TYPE_LOONGARCH_EIOINTC,
|
||||
#define KVM_DEV_TYPE_LOONGARCH_EIOINTC KVM_DEV_TYPE_LOONGARCH_EIOINTC
|
||||
KVM_DEV_TYPE_LOONGARCH_PCHPIC,
|
||||
#define KVM_DEV_TYPE_LOONGARCH_PCHPIC KVM_DEV_TYPE_LOONGARCH_PCHPIC
|
||||
|
||||
KVM_DEV_TYPE_MAX,
|
||||
|
||||
};
|
||||
|
||||
struct kvm_vfio_spapr_tce {
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@
|
|||
#define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18)
|
||||
#define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19)
|
||||
#define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(20)
|
||||
#define PSCI_1_3_FN_SYSTEM_OFF2 PSCI_0_2_FN(21)
|
||||
|
||||
#define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12)
|
||||
#define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13)
|
||||
|
|
@ -68,6 +69,7 @@
|
|||
|
||||
#define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18)
|
||||
#define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(20)
|
||||
#define PSCI_1_3_FN64_SYSTEM_OFF2 PSCI_0_2_FN64(21)
|
||||
|
||||
/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
|
||||
#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff
|
||||
|
|
@ -100,6 +102,9 @@
|
|||
#define PSCI_1_1_RESET_TYPE_SYSTEM_WARM_RESET 0
|
||||
#define PSCI_1_1_RESET_TYPE_VENDOR_START 0x80000000U
|
||||
|
||||
/* PSCI v1.3 hibernate type for SYSTEM_OFF2 */
|
||||
#define PSCI_1_3_OFF_TYPE_HIBERNATE_OFF BIT(0)
|
||||
|
||||
/* PSCI version decoding (independent of PSCI version) */
|
||||
#define PSCI_VERSION_MAJOR_SHIFT 16
|
||||
#define PSCI_VERSION_MINOR_MASK \
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
#define VFIO_EEH 5
|
||||
|
||||
/* Two-stage IOMMU */
|
||||
#define VFIO_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
|
||||
#define __VFIO_RESERVED_TYPE1_NESTING_IOMMU 6 /* Implies v2 */
|
||||
|
||||
#define VFIO_SPAPR_TCE_v2_IOMMU 7
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue