* Fix s390x CPU reconfiguration information in the SCLP facility map

* Fix condition code problem in the CLC and LAALG instruction
 * Fix ordering of the new s390x topology list entries
 * Add some more files to the MAINTAINERS file
 * Allow newer versions of Tesseract in the m68k nextcube test
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Merge tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu into staging

* Fix s390x CPU reconfiguration information in the SCLP facility map
* Fix condition code problem in the CLC and LAALG instruction
* Fix ordering of the new s390x topology list entries
* Add some more files to the MAINTAINERS file
* Allow newer versions of Tesseract in the m68k nextcube test

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# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2023-11-07' of https://gitlab.com/thuth/qemu:
  target/s390x/cpu topology: Fix ordering and creation of TLEs
  tests/tcg/s390x: Test ADD LOGICAL WITH CARRY
  tests/tcg/s390x: Test LAALG with negative cc_src
  target/s390x: Fix LAALG not updating cc_src
  tests/tcg/s390x: Test CLC with inaccessible second operand
  target/s390x: Fix CLC corrupting cc_src
  target/s390x/cpu_models: Use 'first_cpu' in s390_get_feat_block()
  s390/sclp: fix SCLP facility map
  tests/avocado: Allow newer versions of tesseract in the nextcube test
  MAINTAINERS: Add artist.c to the hppa machine section
  MAINTAINERS: Add the virtio-gpu documentation to the corresponding section

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-08 20:34:36 +08:00
commit 44ad47b758
12 changed files with 271 additions and 30 deletions

View file

@ -196,11 +196,7 @@ uint32_t s390_get_ibc_val(void)
void s390_get_feat_block(S390FeatType type, uint8_t *data)
{
static S390CPU *cpu;
if (!cpu) {
cpu = S390_CPU(qemu_get_cpu(0));
}
S390CPU *cpu = S390_CPU(first_cpu);
if (!cpu || !cpu->model) {
return;

View file

@ -210,6 +210,9 @@ static S390TopologyId s390_topology_from_cpu(S390CPU *cpu)
static int s390_topology_id_cmp(const S390TopologyId *l,
const S390TopologyId *r)
{
int l_polarization = l->vertical ? l->entitlement : 0;
int r_polarization = r->vertical ? r->entitlement : 0;
/*
* lexical order, compare less significant values only if more significant
* ones are equal
@ -219,9 +222,8 @@ static int s390_topology_id_cmp(const S390TopologyId *l,
l->book - r->book ?:
l->socket - r->socket ?:
l->type - r->type ?:
/* logic is inverted for the next three */
r->vertical - l->vertical ?:
r->entitlement - l->entitlement ?:
/* logic is inverted for the next two */
r_polarization - l_polarization ?:
r->dedicated - l->dedicated ?:
l->origin - r->origin;
}

View file

@ -442,7 +442,7 @@
D(0xebe8, LAAG, RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TEUQ)
/* LOAD AND ADD LOGICAL */
D(0xebfa, LAAL, RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_TEUL)
D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa, addu64, MO_TEUQ)
D(0xebea, LAALG, RSY_a, ILA, r3, a2, new, in2_r1, laa_addu64, addu64, MO_TEUQ)
/* LOAD AND AND */
D(0xebf4, LAN, RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_TESL)
D(0xebe4, LANG, RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEUQ)

View file

@ -2007,6 +2007,7 @@ static DisasJumpType op_cksm(DisasContext *s, DisasOps *o)
static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
{
int l = get_field(s, l1);
TCGv_i64 src;
TCGv_i32 vl;
MemOp mop;
@ -2016,9 +2017,11 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
case 4:
case 8:
mop = ctz32(l + 1) | MO_TE;
tcg_gen_qemu_ld_tl(cc_src, o->addr1, get_mem_index(s), mop);
/* Do not update cc_src yet: loading cc_dst may cause an exception. */
src = tcg_temp_new_i64();
tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop);
tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);
gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, src, cc_dst);
return DISAS_NEXT;
default:
vl = tcg_constant_i32(l);
@ -2674,17 +2677,32 @@ static DisasJumpType op_kxb(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
static DisasJumpType op_laa(DisasContext *s, DisasOps *o)
static DisasJumpType help_laa(DisasContext *s, DisasOps *o, bool addu64)
{
/* The real output is indeed the original value in memory;
recompute the addition for the computation of CC. */
tcg_gen_atomic_fetch_add_i64(o->in2, o->in2, o->in1, get_mem_index(s),
s->insn->data | MO_ALIGN);
/* However, we need to recompute the addition for setting CC. */
tcg_gen_add_i64(o->out, o->in1, o->in2);
if (addu64) {
tcg_gen_movi_i64(cc_src, 0);
tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);
} else {
tcg_gen_add_i64(o->out, o->in1, o->in2);
}
return DISAS_NEXT;
}
static DisasJumpType op_laa(DisasContext *s, DisasOps *o)
{
return help_laa(s, o, false);
}
static DisasJumpType op_laa_addu64(DisasContext *s, DisasOps *o)
{
return help_laa(s, o, true);
}
static DisasJumpType op_lan(DisasContext *s, DisasOps *o)
{
/* The real output is indeed the original value in memory;