mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 01:03:55 -06:00
hw: arm: allwinner-r40: Add i2c0 device
TWI(i2c) is designed to be used as an interface between CPU host and the serial 2-Wire bus. It can support all standard 2-Wire transfer, can be operated in standard mode(100kbit/s) or fast-mode, supporting data rate up to 400kbit/s. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
d1e409c583
commit
44814e210a
2 changed files with 13 additions and 1 deletions
|
@ -26,6 +26,7 @@
|
|||
#include "hw/intc/arm_gic.h"
|
||||
#include "hw/sd/allwinner-sdhost.h"
|
||||
#include "hw/misc/allwinner-r40-ccu.h"
|
||||
#include "hw/i2c/allwinner-i2c.h"
|
||||
#include "target/arm/cpu.h"
|
||||
#include "sysemu/block-backend.h"
|
||||
|
||||
|
@ -48,6 +49,7 @@ enum {
|
|||
AW_R40_DEV_UART5,
|
||||
AW_R40_DEV_UART6,
|
||||
AW_R40_DEV_UART7,
|
||||
AW_R40_DEV_TWI0,
|
||||
AW_R40_DEV_GIC_DIST,
|
||||
AW_R40_DEV_GIC_CPU,
|
||||
AW_R40_DEV_GIC_HYP,
|
||||
|
@ -89,6 +91,7 @@ struct AwR40State {
|
|||
AwA10PITState timer;
|
||||
AwSdHostState mmc[AW_R40_NUM_MMCS];
|
||||
AwR40ClockCtlState ccu;
|
||||
AWI2CState i2c0;
|
||||
GICState gic;
|
||||
MemoryRegion sram_a1;
|
||||
MemoryRegion sram_a2;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue