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riscv: Unify Qemu's reset vector code path

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Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.

Move it to common function and let all the machines use the common function.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-2-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2020-07-01 11:39:46 -07:00 • committed by Alistair Francis
parent 2c44bbf32c
commit 43cf723adc
5 changed files with 54 additions and 76 deletions
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2
include/hw/riscv/boot.h
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@ -35,5 +35,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base,
hwaddr rom_size, void *fdt);
#endif /* RISCV_BOOT_H */