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target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT

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Rather than look for the combination of DISAS_NEXT with a separate
variable, go ahead and set is_jmp to the desired state.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-31 09:38:45 -07:00
parent f6278ca969
commit 43b3413466
1 changed files with 10 additions and 24 deletions
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34
target/microblaze/translate.c
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@ -70,7 +70,6 @@ typedef struct DisasContext {
/* Decoder. */ /* Decoder. */
uint32_t ext_imm; uint32_t ext_imm;
unsigned int cpustate_changed;
unsigned int tb_flags; unsigned int tb_flags;
unsigned int tb_flags_to_set; unsigned int tb_flags_to_set;
int mem_index; int mem_index;
@ -1255,7 +1254,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
* *
* Therefore, choose to end the TB always. * Therefore, choose to end the TB always.
*/ */
dc->cpustate_changed = 1; dc->base.is_jmp = DISAS_EXIT_NEXT;
return true; return true;
} }
@ -1307,19 +1306,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
tcg_temp_free_i32(t); tcg_temp_free_i32(t);
} }
#ifndef CONFIG_USER_ONLY
static void msr_write(DisasContext *dc, TCGv_i32 v)
{
dc->cpustate_changed = 1;
/* Install MSR_C. */
tcg_gen_extract_i32(cpu_msr_c, v, 2, 1);
/* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */
tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR));
}
#endif
static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
{ {
uint32_t imm = arg->imm; uint32_t imm = arg->imm;
@ -1352,7 +1338,7 @@ static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
} else { } else {
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm); tcg_gen_andi_i32(cpu_msr, cpu_msr, ~imm);
} }
dc->cpustate_changed = 1; dc->base.is_jmp = DISAS_EXIT_NEXT;
} }
return true; return true;
} }
@ -1385,7 +1371,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
TCGv_i32 src = reg_for_read(dc, arg->ra); TCGv_i32 src = reg_for_read(dc, arg->ra);
switch (arg->rs) { switch (arg->rs) {
case SR_MSR: case SR_MSR:
msr_write(dc, src); /* Install MSR_C. */
tcg_gen_extract_i32(cpu_msr_c, src, 2, 1);
/*
* Clear MSR_C and MSR_CC;
* MSR_PVR is not writable, and is always clear.
*/
tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR));
break; break;
case SR_FSR: case SR_FSR:
tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr));
@ -1417,7 +1409,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs); qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs);
return true; return true;
} }
dc->cpustate_changed = 1; dc->base.is_jmp = DISAS_EXIT_NEXT;
return true; return true;
#endif #endif
} }
@ -1629,7 +1621,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
dc->cpu = cpu; dc->cpu = cpu;
dc->tb_flags = dc->base.tb->flags; dc->tb_flags = dc->base.tb->flags;
dc->cpustate_changed = 0;
dc->ext_imm = dc->base.tb->cs_base; dc->ext_imm = dc->base.tb->cs_base;
dc->r0 = NULL; dc->r0 = NULL;
dc->r0_set = false; dc->r0_set = false;
@ -1714,11 +1705,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
} }
dc->base.is_jmp = DISAS_JUMP; dc->base.is_jmp = DISAS_JUMP;
} }
/* Force an exit if the per-tb cpu state has changed. */
if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) {
dc->base.is_jmp = DISAS_EXIT_NEXT;
}
} }
static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)