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target/riscv: Add stimecmp support

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stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2022-08-24 15:13:56 -07:00 • committed by Alistair Francis
parent 7cbcc538f4
commit 43888c2f18
8 changed files with 235 additions and 1 deletions
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4
target/riscv/cpu_bits.h
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@ -206,6 +206,10 @@
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
/* Sstc supervisor CSRs */
#define CSR_STIMECMP 0x14D
#define CSR_STIMECMPH 0x15D
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180