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target/riscv: Update default priority table for local interrupts

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The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
   and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
   (not mandatory) priority assignments.

We update the default priority table and hviprio mapping as-per above.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-06-16 08:45:43 +05:30 • committed by Alistair Francis
parent df01af337f
commit 435774992e
2 changed files with 62 additions and 66 deletions
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2
target/riscv/cpu_bits.h
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@ -774,7 +774,7 @@ typedef enum RISCVException {
#define IPRIO_IRQ_BITS 8
#define IPRIO_MMAXIPRIO 255
#define IPRIO_DEFAULT_UPPER 4
#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 24)
#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12)
#define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE
#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3)
#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3)