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disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. The rotate amount of vror.vi is defined by combining seperated bits. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231026151828.754279-13-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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ea363626ff
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2 changed files with 14 additions and 1 deletions
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@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst)
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return (inst << 34) >> 54;
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return (inst << 34) >> 54;
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}
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}
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static uint32_t operand_vzimm6(rv_inst inst)
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{
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return ((inst << 37) >> 63) << 5 |
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((inst << 44) >> 59);
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}
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static uint32_t operand_bs(rv_inst inst)
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static uint32_t operand_bs(rv_inst inst)
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{
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{
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return (inst << 32) >> 62;
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return (inst << 32) >> 62;
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@ -4393,6 +4399,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
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dec->imm = operand_vimm(inst);
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dec->imm = operand_vimm(inst);
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dec->vm = operand_vm(inst);
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dec->vm = operand_vm(inst);
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break;
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break;
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case rv_codec_vror_vi:
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dec->rd = operand_rd(inst);
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dec->rs2 = operand_rs2(inst);
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dec->imm = operand_vzimm6(inst);
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dec->vm = operand_vm(inst);
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break;
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case rv_codec_vsetvli:
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case rv_codec_vsetvli:
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dec->rd = operand_rd(inst);
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dec->rd = operand_rd(inst);
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dec->rs1 = operand_rs1(inst);
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dec->rs1 = operand_rs1(inst);
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@ -4677,7 +4689,7 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
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append(buf, tmp, buflen);
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append(buf, tmp, buflen);
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break;
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break;
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case 'u':
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case 'u':
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snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
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snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b111111));
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append(buf, tmp, buflen);
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append(buf, tmp, buflen);
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break;
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break;
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case 'j':
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case 'j':
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@ -152,6 +152,7 @@ typedef enum {
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rv_codec_v_i,
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rv_codec_v_i,
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rv_codec_vsetvli,
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rv_codec_vsetvli,
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rv_codec_vsetivli,
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rv_codec_vsetivli,
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rv_codec_vror_vi,
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rv_codec_zcb_ext,
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rv_codec_zcb_ext,
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rv_codec_zcb_mul,
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rv_codec_zcb_mul,
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rv_codec_zcb_lb,
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rv_codec_zcb_lb,
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