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target/arm: Introduce fp_access_check_vector_hsd

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Provide a simple way to check for float64, float32, and float16
support vs vector width, as well as the fpu enabled.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:48 -06:00 • committed by Peter Maydell
parent 648e654efa
commit 43218f2346
1 changed files with 54 additions and 81 deletions
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135
target/arm/tcg/translate-a64.c
View file

@ -1260,6 +1260,28 @@ static int fp_access_check_scalar_hsd(DisasContext *s, MemOp esz)
return fp_access_check(s);
}
/* Likewise, but vector MO_64 must have two elements. */
static int fp_access_check_vector_hsd(DisasContext *s, bool is_q, MemOp esz)
{
switch (esz) {
case MO_64:
if (!is_q) {
return -1;
}
break;
case MO_32:
break;
case MO_16:
if (!dc_isar_feature(aa64_fp16, s)) {
return -1;
}
break;
default:
return -1;
}
return fp_access_check(s);
}
/*
* Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
@ -5420,27 +5442,14 @@ static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, int data,
gen_helper_gvec_3_ptr * const fns[3])
{
MemOp esz = a->esz;
int check = fp_access_check_vector_hsd(s, a->q, esz);
switch (esz) {
case MO_64:
if (!a->q) {
return false;
}
break;
case MO_32:
break;
case MO_16:
if (!dc_isar_feature(aa64_fp16, s)) {
return false;
}
break;
default:
return false;
}
if (fp_access_check(s)) {
gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
esz == MO_16, data, fns[esz - 1]);
if (check <= 0) {
return check == 0;
}
gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
esz == MO_16, data, fns[esz - 1]);
return true;
}
@ -5768,34 +5777,24 @@ TRANS_FEAT(FCADD_270, aa64_fcma, do_fp3_vector, a, 1, f_vector_fcadd)
static bool trans_FCMLA_v(DisasContext *s, arg_FCMLA_v *a)
{
gen_helper_gvec_4_ptr *fn;
static gen_helper_gvec_4_ptr * const fn[] = {
[MO_16] = gen_helper_gvec_fcmlah,
[MO_32] = gen_helper_gvec_fcmlas,
[MO_64] = gen_helper_gvec_fcmlad,
};
int check;
if (!dc_isar_feature(aa64_fcma, s)) {
return false;
}
switch (a->esz) {
case MO_64:
if (!a->q) {
return false;
}
fn = gen_helper_gvec_fcmlad;
break;
case MO_32:
fn = gen_helper_gvec_fcmlas;
break;
case MO_16:
if (!dc_isar_feature(aa64_fp16, s)) {
return false;
}
fn = gen_helper_gvec_fcmlah;
break;
default:
return false;
}
if (fp_access_check(s)) {
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
a->esz == MO_16, a->rot, fn);
check = fp_access_check_vector_hsd(s, a->q, a->esz);
if (check <= 0) {
return check == 0;
}
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
a->esz == MO_16, a->rot, fn[a->esz]);
return true;
}
@ -6337,27 +6336,14 @@ static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a,
gen_helper_gvec_3_ptr * const fns[3])
{
MemOp esz = a->esz;
int check = fp_access_check_vector_hsd(s, a->q, esz);
switch (esz) {
case MO_64:
if (!a->q) {
return false;
}
break;
case MO_32:
break;
case MO_16:
if (!dc_isar_feature(aa64_fp16, s)) {
return false;
}
break;
default:
g_assert_not_reached();
}
if (fp_access_check(s)) {
gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
esz == MO_16, a->idx, fns[esz - 1]);
if (check <= 0) {
return check == 0;
}
gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
esz == MO_16, a->idx, fns[esz - 1]);
return true;
}
@ -6383,28 +6369,15 @@ static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool neg)
gen_helper_gvec_fmla_idx_d,
};
MemOp esz = a->esz;
int check = fp_access_check_vector_hsd(s, a->q, esz);
switch (esz) {
case MO_64:
if (!a->q) {
return false;
}
break;
case MO_32:
break;
case MO_16:
if (!dc_isar_feature(aa64_fp16, s)) {
return false;
}
break;
default:
g_assert_not_reached();
}
if (fp_access_check(s)) {
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
esz == MO_16, (a->idx << 1) | neg,
fns[esz - 1]);
if (check <= 0) {
return check == 0;
}
gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
esz == MO_16, (a->idx << 1) | neg,
fns[esz - 1]);
return true;
}