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riscv: spelling fixes

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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Michael Tokarev 2023-07-14 14:19:10 +03:00
parent 6c67d98c4a
commit 42fe74998c
11 changed files with 21 additions and 21 deletions
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4
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2240,7 +2240,7 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)
*
* If SEW < FLEN, check whether input fp register is a valid
* NaN-boxed value, in which case the least-significant SEW bits
* of the f regsiter are used, else the canonical NaN value is used.
* of the f register are used, else the canonical NaN value is used.
*/
static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
{
@ -3282,7 +3282,7 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
}
}
/* offset of the idx element with base regsiter r */
/* offset of the idx element with base register r */
static uint32_t endian_ofs(DisasContext *s, int r, int idx)
{
#if HOST_BIG_ENDIAN