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RISC-V: Remove unused class definitions

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Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Michael Clark 2018-03-04 13:27:37 +13:00
parent b7938980fb
commit 42b3a4b7cc
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9 changed files with 0 additions and 123 deletions
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5
include/hw/riscv/sifive_u.h
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@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
#define TYPE_SIFIVE_U "riscv.sifive_u"
#define SIFIVE_U(obj) \
OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U)
typedef struct SiFiveUState {
/*< private >*/
SysBusDevice parent_obj;