motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 00:03:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

RISC-V: Remove unused class definitions

Browse source 
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Michael Clark 2018-03-04 13:27:37 +13:00
parent b7938980fb
commit 42b3a4b7cc
No known key found for this signature in database
GPG key ID: 6BF1D7B357EF3E4F
9 changed files with 0 additions and 123 deletions
Download patch file Download diff file Expand all files Collapse all files

5
include/hw/riscv/sifive_e.h
View file

@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_E_H
#define HW_SIFIVE_E_H
#define TYPE_SIFIVE_E "riscv.sifive_e"
#define SIFIVE_E(obj) \
OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E)
typedef struct SiFiveEState {
/*< private >*/
SysBusDevice parent_obj;

5
include/hw/riscv/sifive_u.h
View file

@ -19,11 +19,6 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
#define TYPE_SIFIVE_U "riscv.sifive_u"
#define SIFIVE_U(obj) \
OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U)
typedef struct SiFiveUState {
/*< private >*/
SysBusDevice parent_obj;

7
include/hw/riscv/spike.h
View file

@ -19,12 +19,6 @@
#ifndef HW_SPIKE_H
#define HW_SPIKE_H
#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
#define SPIKE(obj) \
OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
@ -35,7 +29,6 @@ typedef struct {
int fdt_size;
} SpikeState;
enum {
SPIKE_MROM,
SPIKE_CLINT,

5
include/hw/riscv/virt.h
View file

@ -19,10 +19,6 @@
#ifndef HW_VIRT_H
#define HW_VIRT_H
#define TYPE_RISCV_VIRT_BOARD "riscv.virt"
#define VIRT(obj) \
OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
@ -45,7 +41,6 @@ enum {
VIRT_DRAM
};
enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */