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RISC-V: Remove unused class definitions

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Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Michael Clark 2018-03-04 13:27:37 +13:00
parent b7938980fb
commit 42b3a4b7cc
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9 changed files with 0 additions and 123 deletions
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25
hw/riscv/sifive_u.c
View file

@ -301,31 +301,6 @@ static void riscv_sifive_u_init(MachineState *machine)
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
}
static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
{
return 0;
}
static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = riscv_sifive_u_sysbus_device_init;
}
static const TypeInfo riscv_sifive_u_device = {
.name = TYPE_SIFIVE_U,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SiFiveUState),
.class_init = riscv_sifive_u_class_init,
};
static void riscv_sifive_u_register_types(void)
{
type_register_static(&riscv_sifive_u_device);
}
type_init(riscv_sifive_u_register_types);
static void riscv_sifive_u_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with SiFive U SDK";