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target/riscv: remove cpu->cfg.ext_e

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Create a new "e" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
replaced with riscv_has_ext(env, RVE).

Remove the old "e" property and 'ext_e' from RISCVCPUConfig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-04-06 15:03:41 -03:00 • committed by Alistair Francis
parent 74828eabf2
commit 427d8e7dd8
3 changed files with 6 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

10
target/riscv/cpu.c
View file

@ -831,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
env->misa_ext_mask = env->misa_ext; env->misa_ext_mask = env->misa_ext;
} }
if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
error_setg(errp, error_setg(errp,
"I and E extensions are incompatible"); "I and E extensions are incompatible");
return; return;
} }
if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
error_setg(errp, error_setg(errp,
"Either I or E extension must be set"); "Either I or E extension must be set");
return; return;
@ -1150,7 +1150,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVI)) { if (riscv_has_ext(env, RVI)) {
ext |= RVI; ext |= RVI;
} }
if (riscv_cpu_cfg(env)->ext_e) { if (riscv_has_ext(env, RVE)) {
ext |= RVE; ext |= RVE;
} }
if (riscv_cpu_cfg(env)->ext_m) { if (riscv_cpu_cfg(env)->ext_m) {
@ -1503,6 +1503,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVF, .enabled = true}, .misa_bit = RVF, .enabled = true},
{.name = "i", .description = "Base integer instruction set", {.name = "i", .description = "Base integer instruction set",
.misa_bit = RVI, .enabled = true}, .misa_bit = RVI, .enabled = true},
{.name = "e", .description = "Base integer instruction set (embedded)",
.misa_bit = RVE, .enabled = false},
}; };
static void riscv_cpu_add_misa_properties(Object *cpu_obj) static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@ -1525,7 +1527,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = { static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */ /* Defaults for standard extensions */
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
@ -1644,7 +1645,6 @@ static void register_cpu_props(Object *obj)
* later on. * later on.
*/ */
if (cpu->env.misa_ext != 0) { if (cpu->env.misa_ext != 0) {
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM; cpu->cfg.ext_m = misa_ext & RVM;
cpu->cfg.ext_v = misa_ext & RVV; cpu->cfg.ext_v = misa_ext & RVV;
cpu->cfg.ext_s = misa_ext & RVS; cpu->cfg.ext_s = misa_ext & RVS;

1
target/riscv/cpu.h
View file

@ -422,7 +422,6 @@ typedef struct {
} RISCVSATPMap; } RISCVSATPMap;
struct RISCVCPUConfig { struct RISCVCPUConfig {
bool ext_e;
bool ext_g; bool ext_g;
bool ext_m; bool ext_m;
bool ext_s; bool ext_s;

2
target/riscv/insn_trans/trans_rvzce.c.inc
View file

@ -117,7 +117,7 @@ static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist)
{ {
uint32_t reg_bitmap = 0; uint32_t reg_bitmap = 0;
if (ctx->cfg_ptr->ext_e && rlist > 6) { if (has_ext(ctx, RVE) && rlist > 6) {
return 0; return 0;
} }