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RISC-V: Update CSR and interrupt definitions

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* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode interrupts.
* Remove erroneous until comments on machine mode interrupts.
* Move together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.

Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Michael Clark 2018-03-06 10:51:53 +13:00 • committed by Palmer Dabbelt
parent df354dd410
commit 426f03482c
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3 changed files with 363 additions and 314 deletions
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6
target/riscv/cpu.c
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@ -74,8 +74,10 @@ const char * const riscv_intr_names[] = {
"s_external",
"h_external",
"m_external",
"coprocessor",
"host"
"reserved",
"reserved",
"reserved",
"reserved"
};
typedef struct RISCVCPUInfo {