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linux-headers: Update to Linux v6.14-rc3
Update headers to retrieve the latest KVM caps for RISC-V. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250221153758.652078-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
Alistair Francis
parent
2c1b421440
commit
421ee1ec6f
13 changed files with 146 additions and 35 deletions
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@ -681,6 +681,8 @@ enum ethtool_link_ext_substate_module {
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* @ETH_SS_STATS_ETH_MAC: names of IEEE 802.3 MAC statistics
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* @ETH_SS_STATS_ETH_CTRL: names of IEEE 802.3 MAC Control statistics
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* @ETH_SS_STATS_RMON: names of RMON statistics
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* @ETH_SS_STATS_PHY: names of PHY(dev) statistics
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* @ETH_SS_TS_FLAGS: hardware timestamping flags
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*
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* @ETH_SS_COUNT: number of defined string sets
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*/
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@ -706,6 +708,8 @@ enum ethtool_stringset {
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ETH_SS_STATS_ETH_MAC,
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ETH_SS_STATS_ETH_CTRL,
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ETH_SS_STATS_RMON,
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ETH_SS_STATS_PHY,
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ETH_SS_TS_FLAGS,
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/* add new constants above here */
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ETH_SS_COUNT
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@ -220,6 +220,15 @@
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*
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* 7.41
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* - add FUSE_ALLOW_IDMAP
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* 7.42
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* - Add FUSE_OVER_IO_URING and all other io-uring related flags and data
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* structures:
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* - struct fuse_uring_ent_in_out
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* - struct fuse_uring_req_header
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* - struct fuse_uring_cmd_req
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* - FUSE_URING_IN_OUT_HEADER_SZ
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* - FUSE_URING_OP_IN_OUT_SZ
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* - enum fuse_uring_cmd
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*/
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#ifndef _LINUX_FUSE_H
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@ -251,7 +260,7 @@
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#define FUSE_KERNEL_VERSION 7
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/** Minor version number of this interface */
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#define FUSE_KERNEL_MINOR_VERSION 41
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#define FUSE_KERNEL_MINOR_VERSION 42
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/** The node ID of the root inode */
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#define FUSE_ROOT_ID 1
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@ -421,6 +430,7 @@ struct fuse_file_lock {
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* FUSE_HAS_RESEND: kernel supports resending pending requests, and the high bit
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* of the request ID indicates resend requests
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* FUSE_ALLOW_IDMAP: allow creation of idmapped mounts
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* FUSE_OVER_IO_URING: Indicate that client supports io-uring
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*/
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#define FUSE_ASYNC_READ (1 << 0)
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#define FUSE_POSIX_LOCKS (1 << 1)
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@ -467,6 +477,7 @@ struct fuse_file_lock {
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/* Obsolete alias for FUSE_DIRECT_IO_ALLOW_MMAP */
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#define FUSE_DIRECT_IO_RELAX FUSE_DIRECT_IO_ALLOW_MMAP
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#define FUSE_ALLOW_IDMAP (1ULL << 40)
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#define FUSE_OVER_IO_URING (1ULL << 41)
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/**
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* CUSE INIT request/reply flags
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@ -1202,4 +1213,67 @@ struct fuse_supp_groups {
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uint32_t groups[];
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};
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/**
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* Size of the ring buffer header
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*/
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#define FUSE_URING_IN_OUT_HEADER_SZ 128
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#define FUSE_URING_OP_IN_OUT_SZ 128
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/* Used as part of the fuse_uring_req_header */
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struct fuse_uring_ent_in_out {
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uint64_t flags;
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/*
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* commit ID to be used in a reply to a ring request (see also
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* struct fuse_uring_cmd_req)
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*/
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uint64_t commit_id;
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/* size of user payload buffer */
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uint32_t payload_sz;
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uint32_t padding;
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uint64_t reserved;
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};
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/**
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* Header for all fuse-io-uring requests
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*/
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struct fuse_uring_req_header {
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/* struct fuse_in_header / struct fuse_out_header */
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char in_out[FUSE_URING_IN_OUT_HEADER_SZ];
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/* per op code header */
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char op_in[FUSE_URING_OP_IN_OUT_SZ];
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struct fuse_uring_ent_in_out ring_ent_in_out;
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};
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/**
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* sqe commands to the kernel
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*/
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enum fuse_uring_cmd {
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FUSE_IO_URING_CMD_INVALID = 0,
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/* register the request buffer and fetch a fuse request */
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FUSE_IO_URING_CMD_REGISTER = 1,
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/* commit fuse request result and fetch next request */
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FUSE_IO_URING_CMD_COMMIT_AND_FETCH = 2,
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};
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/**
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* In the 80B command area of the SQE.
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*/
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struct fuse_uring_cmd_req {
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uint64_t flags;
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/* entry identifier for commits */
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uint64_t commit_id;
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/* queue the command is for (queue index) */
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uint16_t qid;
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uint8_t padding[6];
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};
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#endif /* _LINUX_FUSE_H */
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@ -519,6 +519,7 @@
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#define KEY_NOTIFICATION_CENTER 0x1bc /* Show/hide the notification center */
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#define KEY_PICKUP_PHONE 0x1bd /* Answer incoming call */
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#define KEY_HANGUP_PHONE 0x1be /* Decline incoming call */
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#define KEY_LINK_PHONE 0x1bf /* AL Phone Syncing */
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#define KEY_DEL_EOL 0x1c0
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#define KEY_DEL_EOS 0x1c1
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@ -533,7 +533,7 @@
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#define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */
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#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */
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#define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
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#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
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#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Max Link Speed (prior to PCIe r3.0: Supported Link Speeds) */
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#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
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#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
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#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
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@ -665,6 +665,7 @@
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
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#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
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#define PCI_EXP_DEVCAP2_EE_PREFIX_MAX 0x00c00000 /* Max End-End TLP Prefixes */
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#define PCI_EXP_DEVCTL2 0x28 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
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@ -789,10 +790,11 @@
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/* Same bits as above */
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#define PCI_ERR_CAP 0x18 /* Advanced Error Capabilities & Ctrl*/
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#define PCI_ERR_CAP_FEP(x) ((x) & 0x1f) /* First Error Pointer */
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#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
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#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
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#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
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#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
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#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
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#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
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#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
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#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
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#define PCI_ERR_CAP_PREFIX_LOG_PRESENT 0x00000800 /* TLP Prefix Log Present */
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#define PCI_ERR_HEADER_LOG 0x1c /* Header Log Register (16 bytes) */
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#define PCI_ERR_ROOT_COMMAND 0x2c /* Root Error Command */
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#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
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@ -808,6 +810,7 @@
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#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
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#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
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#define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */
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#define PCI_ERR_PREFIX_LOG 0x38 /* TLP Prefix LOG Register (up to 16 bytes) */
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/* Virtual Channel */
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#define PCI_VC_PORT_CAP1 0x04
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@ -1001,9 +1004,6 @@
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#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
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#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
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#define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */
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#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */
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/* SATA capability */
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#define PCI_SATA_REGS 4 /* SATA REGs specifier */
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#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
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@ -116,6 +116,8 @@
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#define VIRTIO_PCI_CAP_PCI_CFG 5
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/* Additional shared memory capability */
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#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
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/* PCI vendor data configuration */
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#define VIRTIO_PCI_CAP_VENDOR_CFG 9
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/* This is the PCI capability header: */
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struct virtio_pci_cap {
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@ -130,6 +132,18 @@ struct virtio_pci_cap {
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uint32_t length; /* Length of the structure, in bytes. */
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};
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/* This is the PCI vendor data capability header: */
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struct virtio_pci_vndr_data {
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uint8_t cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
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uint8_t cap_next; /* Generic PCI field: next ptr. */
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uint8_t cap_len; /* Generic PCI field: capability length */
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uint8_t cfg_type; /* Identifies the structure. */
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uint16_t vendor_id; /* Identifies the vendor-specific format. */
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/* For Vendor Definition */
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/* Pads structure to a multiple of 4 bytes */
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/* Reads must not have side effects */
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};
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struct virtio_pci_cap64 {
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struct virtio_pci_cap cap;
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uint32_t offset_hi; /* Most sig 32 bits of offset */
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