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hw/arm/armsse: Introduce SSE subsystem version property
We model Arm "Subsystems for Embedded" SoC subsystems using generic code which is split into various sub-devices which are configurable by QOM properties to handle the behaviour differences between the SSE subsystems we implement. Currently the only sub-device which needs to change is the IOTKIT_SYSCTL device, and we do this with a mix of properties that directly specify divergent behaviours (eg CPUWAIT_RST) and passing it the SYS_VERSION register value as a way for it to distinguish IoTKit from SSE-200. The "pass SYS_VERSION" approach is already a bit hacky, since the IOTKIT_SYSCTL device has to know that the different part of the register value happens to be bits [31:28]. For SSE-300 this register is renamed SOC_IDENTITY and has a different format entirely, all of whose fields can be configured by the SoC integrator when they integrate the SSE into their SoC, and so "pass SYS_VERSION" breaks down completely. Switch to using a simple integer property representing an internal-to-QEMU enumeration of the SSE flavour. For the moment we only need this in IOTKIT_SYSCTL, but as we add SSE-300 support a few of the other devices will also need to know. We define and permit a value for the SSE-300 so we can start using it in subsequent commits which add SSE-300 support. The now-redundant is_sse200 flag in IoTKitSysCtl will be removed in the following commit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-6-peter.maydell@linaro.org
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4 changed files with 58 additions and 10 deletions
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@ -17,9 +17,8 @@
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* "system control register" blocks.
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*
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* QEMU interface:
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* + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
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* system information block of the SSE
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* (used to identify whether to provide SSE-200-only registers)
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* + QOM property "sse-version": indicates which SSE version this is part of
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* (used to identify whether to provide SSE-200-only registers, etc)
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* + sysbus MMIO region 0: the system information register bank
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* + sysbus MMIO region 1: the system control register bank
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*/
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@ -61,7 +60,7 @@ struct IoTKitSysCtl {
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uint32_t pdcm_pd_sram3_sense;
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/* Properties */
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uint32_t sys_version;
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uint32_t sse_version;
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uint32_t cpuwait_rst;
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uint32_t initsvtor0_rst;
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uint32_t initsvtor1_rst;
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