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tcg-mips: Rearrange register allocation

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Use FP (also known as S8) as a normal call-saved register.

Include T0 in the allocation order and call-clobbered list
even though it's currently used as a TCG temporary.

Put the argument registers at the end of the allocation order.

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-04-15 09:03:59 -07:00
parent fbef2cc80f
commit 418839044e
2 changed files with 19 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

22
tcg/mips/tcg-target.c
View file

@ -67,13 +67,14 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"k1", "k1",
"gp", "gp",
"sp", "sp",
"fp", "s8",
"ra", "ra",
}; };
#endif #endif
/* check if we really need so many registers :P */ /* check if we really need so many registers :P */
static const TCGReg tcg_target_reg_alloc_order[] = { static const TCGReg tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
TCG_REG_S0, TCG_REG_S0,
TCG_REG_S1, TCG_REG_S1,
TCG_REG_S2, TCG_REG_S2,
@ -82,6 +83,10 @@ static const TCGReg tcg_target_reg_alloc_order[] = {
TCG_REG_S5, TCG_REG_S5,
TCG_REG_S6, TCG_REG_S6,
TCG_REG_S7, TCG_REG_S7,
TCG_REG_S8,
/* Call clobbered registers. */
TCG_REG_T0,
TCG_REG_T1, TCG_REG_T1,
TCG_REG_T2, TCG_REG_T2,
TCG_REG_T3, TCG_REG_T3,
@ -91,12 +96,14 @@ static const TCGReg tcg_target_reg_alloc_order[] = {
TCG_REG_T7, TCG_REG_T7,
TCG_REG_T8, TCG_REG_T8,
TCG_REG_T9, TCG_REG_T9,
TCG_REG_A0, TCG_REG_V1,
TCG_REG_A1,
TCG_REG_A2,
TCG_REG_A3,
TCG_REG_V0, TCG_REG_V0,
TCG_REG_V1
/* Argument registers, opposite order of allocation. */
TCG_REG_A3,
TCG_REG_A2,
TCG_REG_A1,
TCG_REG_A0,
}; };
static const TCGReg tcg_target_call_iarg_regs[4] = { static const TCGReg tcg_target_call_iarg_regs[4] = {
@ -1646,7 +1653,7 @@ static int tcg_target_callee_save_regs[] = {
TCG_REG_S5, TCG_REG_S5,
TCG_REG_S6, TCG_REG_S6,
TCG_REG_S7, TCG_REG_S7,
TCG_REG_FP, TCG_REG_S8,
TCG_REG_RA, /* should be last for ABI compliance */ TCG_REG_RA, /* should be last for ABI compliance */
}; };
@ -1778,6 +1785,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_A1) | (1 << TCG_REG_A1) |
(1 << TCG_REG_A2) | (1 << TCG_REG_A2) |
(1 << TCG_REG_A3) | (1 << TCG_REG_A3) |
(1 << TCG_REG_T0) |
(1 << TCG_REG_T1) | (1 << TCG_REG_T1) |
(1 << TCG_REG_T2) | (1 << TCG_REG_T2) |
(1 << TCG_REG_T3) | (1 << TCG_REG_T3) |

8
tcg/mips/tcg-target.h
View file

@ -60,8 +60,11 @@ typedef enum {
TCG_REG_K1, TCG_REG_K1,
TCG_REG_GP, TCG_REG_GP,
TCG_REG_SP, TCG_REG_SP,
TCG_REG_FP, TCG_REG_S8,
TCG_REG_RA, TCG_REG_RA,
TCG_REG_CALL_STACK = TCG_REG_SP,
TCG_AREG0 = TCG_REG_S0,
} TCGReg; } TCGReg;
#define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_ZERO 0x100
@ -69,7 +72,6 @@ typedef enum {
#define TCG_CT_CONST_S16 0x400 #define TCG_CT_CONST_S16 0x400
/* used for function call generation */ /* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_SP
#define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_STACK_ALIGN 8
#define TCG_TARGET_CALL_STACK_OFFSET 16 #define TCG_TARGET_CALL_STACK_OFFSET 16
#define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_ALIGN_ARGS 1
@ -127,8 +129,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */ #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */ #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
#define TCG_AREG0 TCG_REG_S0
#ifdef __OpenBSD__ #ifdef __OpenBSD__
#include <machine/sysarch.h> #include <machine/sysarch.h>
#else #else