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hw/mem/cxl_type3: Add CXL RAS Error Injection Support.

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CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.

For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
OS. The equivalent feature doesn't exist for correctable errors, so only
one error need be injected at a time.

Note:
 - Header content needs to be manually specified in a fashion that
   matches the specification for what can be in the header for each
   error type.

Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
  "arguments": {
    "path": "/machine/peripheral/cxl-pmem0",
    "errors": [
        {
            "type": "cache-address-parity",
            "header": [ 3, 4]
        },
        {
            "type": "cache-data-parity",
            "header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
        },
        {
            "type": "internal",
            "header": [ 1, 2, 4]
        }
        ]
  }}
...
{ "execute": "cxl-inject-correctable-error",
    "arguments": {
        "path": "/machine/peripheral/cxl-pmem0",
        "type": "physical"
    } }

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230302133709.30373-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2023-03-02 13:37:09 +00:00 • committed by Michael S. Tsirkin
parent 4a295211f7
commit 415442a1b4
9 changed files with 470 additions and 1 deletions
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26
include/hw/cxl/cxl_component.h
View file

@ -65,11 +65,37 @@ CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
#define CXL_RAS_REGISTERS_OFFSET 0x80
#define CXL_RAS_REGISTERS_SIZE 0x58
REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET)
#define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0
#define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1
#define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2
#define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3
#define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4
#define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5
#define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6
#define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7
#define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8
#define CXL_RAS_UNC_ERR_RSVD_ENCODING 9
#define CXL_RAS_UNC_ERR_POISON_RECEIVED 10
#define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11
#define CXL_RAS_UNC_ERR_INTERNAL 14
#define CXL_RAS_UNC_ERR_CXL_IDE_TX 15
#define CXL_RAS_UNC_ERR_CXL_IDE_RX 16
#define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */
REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4)
REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8)
REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
#define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0
#define CXL_RAS_COR_ERR_MEM_DATA_ECC 1
#define CXL_RAS_COR_ERR_CRC_THRESHOLD 2
#define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3
#define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4
#define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5
#define CXL_RAS_COR_ERR_PHYSICAL 6
REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
#define CXL_RAS_ERR_HEADER_NUM 32
/* Offset 0x18 - 0x58 reserved for RAS logs */
/* 8.2.5.10 - CXL Security Capability Structure */