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tcg/s390x: Use register pair allocation for div and mulu2

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Previously we hard-coded R2 and R3.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-10 08:41:15 -07:00
parent aaa90fede5
commit 4143f78dad
3 changed files with 35 additions and 20 deletions
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8
tcg/s390x/tcg-target-con-str.h
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@ -11,13 +11,7 @@
REGS('r', ALL_GENERAL_REGS)
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
REGS('v', ALL_VECTOR_REGS)
/*
* A (single) even/odd pair for division.
* TODO: Add something to the register allocator to allow
* this kind of regno+1 pairing to be done more generally.
*/
REGS('a', 1u << TCG_REG_R2)
REGS('b', 1u << TCG_REG_R3)
REGS('o', 0xaaaa) /* odd numbered general regs */
/*
* Define constraint letters for constants: