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target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M

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Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security
extensions are enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-07 13:54:53 +01:00
parent 45db7ba681
commit 4125e6feb7
4 changed files with 14 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

8
hw/intc/armv7m_nvic.c
View file

@ -604,12 +604,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset;
}
return cpu->env.pmsav8.mair0;
return cpu->env.pmsav8.mair0[attrs.secure];
case 0xdc4: /* MPU_MAIR1 */
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset;
}
return cpu->env.pmsav8.mair1;
return cpu->env.pmsav8.mair1[attrs.secure];
default:
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
@ -826,7 +826,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
if (cpu->pmsav7_dregion) {
/* Register is RES0 if no MPU regions are implemented */
cpu->env.pmsav8.mair0 = value;
cpu->env.pmsav8.mair0[attrs.secure] = value;
}
/* We don't need to do anything else because memory attributes
* only affect cacheability, and we don't implement caching.
@ -838,7 +838,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
if (cpu->pmsav7_dregion) {
/* Register is RES0 if no MPU regions are implemented */
cpu->env.pmsav8.mair1 = value;
cpu->env.pmsav8.mair1[attrs.secure] = value;
}
/* We don't need to do anything else because memory attributes
* only affect cacheability, and we don't implement caching.